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	This directory contains the VHDL and Behavioral sources of our paper, Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators, presented in the 55th Design Automation Conference 2018. 

	This directory contains the following two folders:

	1.	VHDL
	
	--> This folder contains the following VHDL sources:
	* Accurate: 4x4 multiplier, ternary 8 and 16-bit adders.
	* Approximate: 4x2, 4x4, 8x8 Ca, 8x8 Cc, 16x16 Ca and 16x16 Cc multipliers.

	2.	Behavioral
	
	--> This folder contains the Python-based behavioral models for the following approximate multipliers:
	* 4x2, 4x4, 8x8-Ca, 8x8-Cc, 16x16-Ca and 16x16-Cc

	The adder type for summing the outputs of sub-multipliers for implementing 8x8 and other higher order multipliers can be specified with add flag. 
	* For example:
	Python mult_8x8.py 150 160 add app will multiply 150 with 160 and use approximate addition for the summation of results produced by 4x4 sub-multipliers.

	The VHDL and python-based models can be easily extended to higher order multipliers. Moreover, a thorough design space exploration can be performed with different combinations of proposed multipliers.

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	For questions/suggestions please email Dr. Akash Kumar (akash.kumar@tu-dresden.de) and Salim Ullah (salim.ullah@tu-dresden.de)
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