Karl Friebel |
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Phone Fax Visitor's Address |
Phone: +49 (0)351 463 43710 Fax: +49 (0)351 463 39995 Helmholtzstrasse 18 |
Karl Friebel received his Diploma degree in Computer Science from TU Dresden in December 2020. He wrote his Diploma-Thesis at the Chair for Adaptive Dynamical Systems, centered on using polyhedral modelling for source-to-source compilation as a strategy to improve High-Level Synthesis results for FPGA platforms. While the main focus of his studies has been on hardware design and tooling, Karl gained considerable experience in end-user applications, mainly in the area of scientific computing and fluid dynamics in particular.
After previously collaborating in research at the Chair for Compiler Construction in 2018, Karl continued to concentrate his efforts on improving and proliferating compiler tooling. In February 2021, he joined the chair as research assistant, where he works on the project “EVEREST: Design environment for extreme-scale big data analytics on heterogeneous platforms”, funded by the European Union’s Horizon 2020 research and innovation program under grant agreement no 957269.
It is my personal conviction that the availability and flexibility of compiler tooling dictates the extent to which innovations in hardware design are feasible and/or practically profitable. As a proponent of specialized hardware designs for application-specific tasks, I try to dedicate myself to creating the conditions required to make the hardware platforms of the future more heterogeneous. With most of my expertise focusing towards the interface and software part of the problem, my primary research goal is making compilers more flexible, powerful, and, hopefully, more usable.
In that regard, my current main topics are roughly:
- Designing languages and libraries that bring users and their applications closer together
- Polyhedral modelling and its opportunities and shortcomings in modelling computational kernels
- Using FPGAs (and other custom) acellerators for scientific computing
- Evaluating and developing models for distributing workloads in heterogeneous systems
With a background studying various aspects and applications of scientific simulations, but also having worked in application development in the industry, I realize that it is the use-cases that ultimately make or break my vision. As a result, I strive for at least the intermediate knowledge required to be able to understand them, and consequently evaluate the results that we might produce.
Here, I have specifically acquired interest and experience in these points:
- Particle methods as a common abstraction for implementing general numerical scientific simulations
- Computational mechanics and specifically fluid dynamics as a high-performance application
- Tailoring operating/embedded systems for application-specific guarantees
I feel that most of my work lives from the use it can provide to other people, and so, as I want to be a mediator in that regard, I encourage anyone to approach me if they are interested in bringing some of my vision into their application. On the other hand, I have learned that this kind of work leads to tunnel vision with respect to the approaches chosen, so I welcome all working on similar facets who whish to share their vision with me!
On a side note, as a developer around compilers for more than four years, I may have developed a new sense in code, which draws me to strain the limits of our modern languages and compilers in strive of artificial goals of abstractness and conciseness. If you can relate, I am always keen on seeing that applied elsewhere, so don't hesitate to share your opinion or ask for mine.
2025
- Asif Ali Khan, Hamid Farzaneh, Karl F. A. Friebel, Clément Fournier, Lorenzo Chelini, Jeronimo Castrillon, "CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms" (to appear), Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'25), Association for Computing Machinery, Mar 2025. [Bibtex & Downloads]
CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms
×Reference
Asif Ali Khan, Hamid Farzaneh, Karl F. A. Friebel, Clément Fournier, Lorenzo Chelini, Jeronimo Castrillon, "CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms" (to appear), Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'25), Association for Computing Machinery, Mar 2025.
Bibtex
@InProceedings{khan_asplos25,
author = {Khan, Asif Ali and Farzaneh, Hamid and Friebel, Karl F. A. and Fournier, Clément and Chelini, Lorenzo and Castrillon, Jeronimo},
booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'25)},
title = {CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms},
location = {Rotterdam, The Netherlands},
publisher = {Association for Computing Machinery},
series = {ASPLOS '25},
month = mar,
year = {2025},
}Downloads
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2024
- Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jeronimo Castrillon, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco, Katerina Slaninova, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner, "A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach", Proceedings of the 2024 Design, Automation and Test in Europe Conference (DATE), 6pp, Mar 2024. [Bibtex & Downloads]
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach
×Reference
Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jeronimo Castrillon, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco, Katerina Slaninova, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner, "A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach", Proceedings of the 2024 Design, Automation and Test in Europe Conference (DATE), 6pp, Mar 2024.
Bibtex
@InProceedings{pilato_date24,
author = {Christian Pilato and Subhadeep Banik and Jakub Beránek and Fabien Brocheton and Jeronimo Castrillon and Riccardo Cevasco and Radim Cmar and Serena Curzel and Fabrizio Ferrandi and Karl F. A. Friebel and Antonella Galizia and Matteo Grasso and Paulo Silva and Jan Martinovic and Gianluca Palermo and Michele Paolino and Andrea Parodi and Antonio Parodi and Fabio Pintus and Raphael Polig and David Poulet and Francesco Regazzoni and Burkhard Ringlein and Roberto Rocco and Katerina Slaninova and Tom Slooff and Stephanie Soldavini and Felix Suchert and Mattia Tibaldi and Beat Weiss and Christoph Hagleitner},
booktitle = {Proceedings of the 2024 Design, Automation and Test in Europe Conference (DATE)},
title = {A System Development Kit for Big Data Applications on {FPGA}-based Clusters: The {EVEREST} Approach},
location = {Valencia, Spain},
url = {https://ieeexplore.ieee.org/document/10546518},
pages = {6pp},
series = {DATE'24},
month = mar,
year = {2024},
}Downloads
2403_Pilato_DATE [PDF]
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2023
- Karl F. A. Friebel, Jiahong Bi, Jeronimo Castrillon, "BASE2: An IR for Binary Numeral Types", In Proceeding: 13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023), Association for Computing Machinery, pp. 19–26, New York, NY, USA, Jun 2023. [doi] [Bibtex & Downloads]
BASE2: An IR for Binary Numeral Types
×Reference
Karl F. A. Friebel, Jiahong Bi, Jeronimo Castrillon, "BASE2: An IR for Binary Numeral Types", In Proceeding: 13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023), Association for Computing Machinery, pp. 19–26, New York, NY, USA, Jun 2023. [doi]
Abstract
Custom data types and arbitrary-precision arithmetic are often key for efficient hardware designs on Field Programmable Gate Array (FPGA) platforms. Current end-to-end flows incorporating quantization are not only domain-specific, but also tightly integrated and not repurposable. Abstractions for arbitrary-precision arithmetic are generally vendor-specific, and results are hardly portable across platforms. In this work, we present a new Intermediate Representation (IR), base2, to address the programmability issues of custom data types in reconfigurable hardware. We contextualize our proposal in the greater LLVM (llvm) ecosystem, where we show how existing abstractions can be simplified and unified. We implement base2 in Multi-Level Intermediate Representation (MLIR), which allows it to be used in a variety of existing and future target-agnostic front-ends. We demonstrate the power of our model by applying it to sample kernels and evaluating the accuracy of the result. For these samples, we achieve interoperability with an existing end-to-end High-Level Synthesis (HLS) flow.
Bibtex
@InProceedings{friebel_heart23,
author = {Karl F. A. Friebel and Jiahong Bi and Jeronimo Castrillon},
booktitle = {13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023)},
title = {{BASE2}: An {IR} for Binary Numeral Types},
doi = {10.1145/3597031.3597048},
isbn = {9798400700439},
location = {Kusatsu, Japan},
pages = {19--26},
publisher = {Association for Computing Machinery},
series = {HEART2023},
url = {https://doi.org/10.1145/3597031.3597048},
abstract = {Custom data types and arbitrary-precision arithmetic are often key for efficient hardware designs on Field Programmable Gate Array (FPGA) platforms. Current end-to-end flows incorporating quantization are not only domain-specific, but also tightly integrated and not repurposable. Abstractions for arbitrary-precision arithmetic are generally vendor-specific, and results are hardly portable across platforms. In this work, we present a new Intermediate Representation (IR), base2, to address the programmability issues of custom data types in reconfigurable hardware. We contextualize our proposal in the greater LLVM (llvm) ecosystem, where we show how existing abstractions can be simplified and unified. We implement base2 in Multi-Level Intermediate Representation (MLIR), which allows it to be used in a variety of existing and future target-agnostic front-ends. We demonstrate the power of our model by applying it to sample kernels and evaluating the accuracy of the result. For these samples, we achieve interoperability with an existing end-to-end High-Level Synthesis (HLS) flow.},
address = {New York, NY, USA},
month = jun,
numpages = {8},
year = {2023},
}Downloads
2306_Friebel_HEART [PDF]
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- Stephanie Soldavini, Karl F. A. Friebel, Mattia Tibaldi, Gerald Hempel, Jeronimo Castrillon, Christian Pilato, "Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Association for Computing Machinery, vol. 16, no. 2, New York, NY, USA, Mar 2023. [doi] [Bibtex & Downloads]
Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics
×Reference
Stephanie Soldavini, Karl F. A. Friebel, Mattia Tibaldi, Gerald Hempel, Jeronimo Castrillon, Christian Pilato, "Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Association for Computing Machinery, vol. 16, no. 2, New York, NY, USA, Mar 2023. [doi]
Abstract
Numerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but when applications are memory-bound designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. This development process requires hardware design skills that are uncommon in domain-specific experts. In this paper, we propose an automated tool flow from a domain-specific language (DSL) for tensor expressions to generate massively-parallel accelerators on HBM-equipped FPGAs. Designers can use this flow to integrate and evaluate various compiler or hardware optimizations. We use computational fluid dynamics (CFD) as a paradigmatic example. Our flow starts from the high-level specification of tensor operations and combines an MLIR-based compiler with an in-house hardware generation flow to generate systems with parallel accelerators and a specialized memory architecture that moves data efficiently, aiming at fully exploiting the available CPU-FPGA bandwidth. We simulated applications with millions of elements, achieving up to 103 GFLOPS with one compute unit and custom precision when targeting a Xilinx Alveo U280. Our FPGA implementation is up to 25 \texttimes more energy efficient than expert-crafted Intel CPU implementations.
Bibtex
@Article{friebel_trets23,
author = {Stephanie Soldavini and Karl F. A. Friebel and Mattia Tibaldi and Gerald Hempel and Jeronimo Castrillon and Christian Pilato},
title = {Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics},
doi = {10.1145/3563553},
issn = {1936-7406},
number = {2},
url = {https://doi.org/10.1145/3563553},
volume = {16},
abstract = {Numerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but when applications are memory-bound designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. This development process requires hardware design skills that are uncommon in domain-specific experts. In this paper, we propose an automated tool flow from a domain-specific language (DSL) for tensor expressions to generate massively-parallel accelerators on HBM-equipped FPGAs. Designers can use this flow to integrate and evaluate various compiler or hardware optimizations. We use computational fluid dynamics (CFD) as a paradigmatic example. Our flow starts from the high-level specification of tensor operations and combines an MLIR-based compiler with an in-house hardware generation flow to generate systems with parallel accelerators and a specialized memory architecture that moves data efficiently, aiming at fully exploiting the available CPU-FPGA bandwidth. We simulated applications with millions of elements, achieving up to 103 GFLOPS with one compute unit and custom precision when targeting a Xilinx Alveo U280. Our FPGA implementation is up to 25 \texttimes{} more energy efficient than expert-crafted Intel CPU implementations.},
address = {New York, NY, USA},
articleno = {21},
journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
month = mar,
numpages = {34},
publisher = {Association for Computing Machinery},
year = {2023},
}Downloads
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- Karl F. A. Friebel, Asif Ali Khan, Lorenzo Chelini, Jeronimo Castrillon, "Modelling linear algebra kernels as polyhedral volume operations", In Proceeding: 13th International Workshop on Polyhedral Compilation Techniques (IMPACT'23), co-located with 18th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Jan 2023. [Bibtex & Downloads]
Modelling linear algebra kernels as polyhedral volume operations
×Reference
Karl F. A. Friebel, Asif Ali Khan, Lorenzo Chelini, Jeronimo Castrillon, "Modelling linear algebra kernels as polyhedral volume operations", In Proceeding: 13th International Workshop on Polyhedral Compilation Techniques (IMPACT'23), co-located with 18th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Jan 2023.
Bibtex
@InProceedings{friebel_impact23,
author = {Karl F. A. Friebel and Asif Ali Khan and Lorenzo Chelini and Jeronimo Castrillon},
booktitle = {13th International Workshop on Polyhedral Compilation Techniques (IMPACT'23), co-located with 18th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)},
title = {Modelling linear algebra kernels as polyhedral volume operations},
location = {Toulouse, France},
url = {https://impact-workshop.org/papers/paper10.pdf},
month = jan,
year = {2023},
}Downloads
2301_Friebel_IMPACT [PDF]
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2021
- Karl F. A. Friebel, Stephanie Soldavini, Gerald Hempel, Christian Pilato, Jeronimo Castrillon, "From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics", Proceedings of the 2021 IEEE International Conference on Cluster Computing (CLUSTER) — FPGA for HPC Workshop, pp. 759–766, Sep 2021. [doi] [Bibtex & Downloads]
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics
×Reference
Karl F. A. Friebel, Stephanie Soldavini, Gerald Hempel, Christian Pilato, Jeronimo Castrillon, "From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics", Proceedings of the 2021 IEEE International Conference on Cluster Computing (CLUSTER) — FPGA for HPC Workshop, pp. 759–766, Sep 2021. [doi]
Bibtex
@InProceedings{friebel_fpga4hpc21,
author = {Karl F. A. Friebel and Stephanie Soldavini and Gerald Hempel and Christian Pilato and Jeronimo Castrillon},
booktitle = {Proceedings of the 2021 IEEE International Conference on Cluster Computing (CLUSTER) --- FPGA for HPC Workshop},
title = {From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics},
doi = {10.1109/Cluster48925.2021.00112},
location = {Portland (virtual), OR, USA},
pages = {759--766},
url = {https://ieeexplore.ieee.org/document/9556064},
month = sep,
numpages = {8},
year = {2021},
}Downloads
2109_Friebel_fpga4hpc [PDF]
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