cfaed Seminar Series

Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide significant acceleration in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this presentation, a macro-modeling method for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature are described. Timing and power characterizations for the cells of a digital cell library are provided. The results prove the efficiency of the equivalent inverter approach in modeling complex CMOS gates.