The Tomahawk 2 chip that had its tape out in march came back to our labs. The chip is a heterogeneous multi processor system on chip (MPSoC). A dynamic task scheduling unit, the CoreManager sits at its center, controlling the computation load of numerous processing elements (PEs). A special extension to the programming language C, namely taskC has been developed to provide an easy to use interface for the programmer that abstracts the distributed parallel computation from the available hardware. In taskC the programmer only defines tasks that can potentially are run in parallel to each other. This means that the programmer does not have to know about the underlying hardware. The CoreManager kows about the chips topology and can place generated tasks to available PEs at runtime even if the topology (e.g. the number of PEs) changes during execution. Furthermore, it can even change the topology on its own by changing PE frequency or turning of PEs completely to save power.

For Orchestration path the Tomahawk architecture can also be viewed from a different angle. The tiled architecture consists of a number of tiles each hosting one processor and a network on chip connecting every tile providing a scalable uniform connection throughout the whole chip. With the set of tiles being inhomogeneous this platform makes a good playground for trying out how to deal with heterogeneity in system integration whilst new technologies from other paths are not ready.