- Silicon Nanowire Path
- Carbon Path
- Organic / Polymer Path
- Biomolecular-Assembled Circuits
- Chemical Information Processing Path
- Orchestration Path
- Resilience Path
- CRC 912 (HAEC)
- Biological Systems Path
|Abstract: Modern commodity CPUs are equipped with plentiful ISA extensions, e.g., recent Intel processors contain extensions for vector manipulation (AVX), hardware transactional memory (TSX), memory protection (MPX), and secure computation (SGX). Moreover, current CPU microarchitectures provide abundant processing capabilities such as powerful branch predictors, deep pipelines, and out-of-order execution. In this work, we show how to increase software dependability by leveraging CPU extensions, with the focus on software-based fault tolerance and security for legacy C/C++ programs. For fault tolerance, we build techniques to detect CPU faults utilizing unused IPC resources (∆-Encoding project), and Intel TSX (HAFT) and Intel AVX (Elzar) extension sets. For security, we investigate memory safety using Intel MPX and develop a specialized solution for Intel SGX (SGXBounds).
Abstract: Modern architectures are increasingly making use of a large number of heterogeneous computing units such as FPGAs, GPUs, and specialized accelerators. Currently, these computing units are treated as devices without having direct access to OS services such file-systems, networking, memory management, etc. The primary reason for their poor integration is the missing interface to grant them access to system resources while enforcing proper isolation which is done by the MMU on a standard core.
In order to manage these computing units we are developing a scalable multikernel based on the M3 operating system. M3 does not require a kernel to be run on computing units, but can control and configure them via a single privileged processing element running a kernel. The goal of our work is to extend the M3 design to a multikernel OS approach to make the OS scalable and resilient against failures. In this talk, I will discuss the extended motivation for our project, and important challenges that we need to address including, resource distribution, naming, load balancing and distributed capability management.
|Abstract: Modern in-memory database systems leverage the increasing processor performance and memory density of each new hardware generation. Meanwhile, with each technology node, hardware becomes less reliable and database system designers must start considering multi-bit flips as the norm rather than the exception. AN coding has little to moderate impact on the key performance indicators of database systems: query throughput and query latency. In this talk I present the concepts of AN coding and our enhancements, as well as its integration into the query processing layer of database systems.
|Abstract: Rapid scaling of transistor gate sizes has significantly increased the density of on-chip integrations and paved the way for many-core systems-on-chip with highly improved performances. The design of the interconnection network for these complex systems is a critical one and the network-on-chip (NoC) is now the predominantly adopted interconnect for such large core arrays. However, the performance enhancements of technology scaling come at the cost of reliability as on-chip components particularly the NoC become increasingly prone to faults. Redundancy is the basic approach to fault tolerance and in this talk, we discuss different approaches toward NoC fault tolerance and their results.
|Abstract: Cyber-physical systems (CPS) use distributed feedback loops to control physical processes. Designing practical distributed CPS controllers often benefits from a logically centralized approach, where each node computes the control law locally based on global knowledge of the system state. We present Mixer, an all-to-all communication protocol that enables nodes in a multi-hop low-power wireless network to exchange sizable packets with one another. Mixer harnesses the broadcast nature of the wireless medium and integrates synchronous transmissions with random linear network coding, thereby achieving high resilience against unpredictable packet losses and node failures. Results from real-world experiments demonstrate that Mixer significantly reduces latency compared with the state of the art, while providing similar or higher reliability.
|Abstract: Upcoming technologies will be highly impacted by on-chip device variation, ageing and supply voltage variation. Therefore on-chip timing variations will increase significantly. A full featured set of timing-detection standard cells was designed in a current CMOS technology and can be inserted by a technology independent adapted design flow into any digital design given in a hardware description language during netlist and layout synthesis. Two prototype chips with the developed detector cells in CMOS prove detector functionality and motivate further research.