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One of the biggest challenges to photonic computing is the large chip area of optical components, which constrains the size of practical photonic processors. For example, it is very challenging to scale up silicon-photonic matrix multipliers  beyond 64x64, which is still small by electronics standards. This talk focuses on our group's efforts to circumvent this challenge using an output-stationary dataflow, which makes use of the time dimension to reduce the required chip area from N^2 to N, effectively "squaring" the scalability of photonic systems. First, I report our group's experimental realization [1] of the proposed photoelectric matrix-vector multiplier [2] using an array of individually addressable, injection-locked VCSELs and 3D diffractive optical fan-out. This VCSEL architecture provides the ideal combination of compactness, speed, scalability, and low energy consumption to support large-scale deep learning in the data center. Second, I report on the demonstration of the Netcast protocol for optically accelerated edge computing [3], applicable in situations where data processing is performed on a power- constrained device with an optical link to a server. Using Netcast, where we realize DNN inference at 98.8% accuracy over an 86-km fiber with 3 THz of optical bandwidth at an optical energy consumption of 40 aJ/MAC.