Publications
Orch Publications
2023
- Carlos Escuin, Asif Ali Khan, Pablo Ibáñez-Marín, Teresa Monreal, Jeronimo Castrillon, Víctor Viñals-Yúfera, "Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs", In Proceeding: the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA'23), IEEE Computer Society, pp. 179–192, Los Alamitos, CA, USA, Mar 2023. [doi] [Bibtex & Downloads]
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs
×Reference
Carlos Escuin, Asif Ali Khan, Pablo Ibáñez-Marín, Teresa Monreal, Jeronimo Castrillon, Víctor Viñals-Yúfera, "Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs", In Proceeding: the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA'23), IEEE Computer Society, pp. 179–192, Los Alamitos, CA, USA, Mar 2023. [doi]
Abstract
Emerging non-volatile memory (NVM) technologies can potentially replace large SRAM memories such as the last-level cache (LLC). However, despite recent advances, NVMs suffer from higher write latency and limited write endurance. Recently, NVM-SRAM hybrid LLCs are proposed to combine the best of both worlds. Several policies have been proposed to improve the performance and lifetime of hybrid LLCs by intelligently steering the incoming LLC blocks into either the SRAM or NVM part, regarding the cache behavior of the LLC blocks and the SRAM/NVM device properties. However, these policies neither consider compressing the contents of the cache block nor using partially worn-out NVM cache blocks.This paper proposes new insertion policies for byte-level fault-tolerant hybrid LLCs that collaboratively optimize for lifetime and performance. Specifically, we leverage data compression to utilize partially defective NVM cache entries, thereby improving the LLC hit rate. The key to our approach is to guide the insertion policy by both the reuse properties of the block and the size resulting from its compression. A block is inserted in NVM only if it is a read-reuse block or its compressed size is lower than a threshold. It will be inserted in SRAM if the block is a write-reuse or its compressed size is greater than the threshold. We use set-dueling to tune the compression threshold at runtime. This compression threshold provides a knob to control the NVM write rate and, together with a rule-based mechanism, allows balancing performance and lifetime.Overall, our evaluation shows that, with affordable hardware overheads, the proposed schemes can nearly reach the performance of an SRAM cache with the same associativity while improving lifetime by 17x compared to a hybrid NVM-unaware LLC. Our proposed scheme outperforms the state-of-the-art insertion policies by 9% while achieving a comparative lifetime. The rule-based mechanism shows that by compromising, for instance, 1.1% and 1.9% performance, the NVM lifetime can be further increased by 28% and 44%, respectively.
Bibtex
@InProceedings{escuin_hpca23,
author = {Carlos Escuin and Asif Ali Khan and Pablo Ibáñez-Marín and Teresa Monreal and Jeronimo Castrillon and Víctor Viñals-Yúfera},
booktitle = {the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA'23)},
title = {Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs},
organization = {IEEE},
pages = {179--192},
abstract = {Emerging non-volatile memory (NVM) technologies can potentially replace large SRAM memories such as the last-level cache (LLC). However, despite recent advances, NVMs suffer from higher write latency and limited write endurance. Recently, NVM-SRAM hybrid LLCs are proposed to combine the best of both worlds. Several policies have been proposed to improve the performance and lifetime of hybrid LLCs by intelligently steering the incoming LLC blocks into either the SRAM or NVM part, regarding the cache behavior of the LLC blocks and the SRAM/NVM device properties. However, these policies neither consider compressing the contents of the cache block nor using partially worn-out NVM cache blocks.This paper proposes new insertion policies for byte-level fault-tolerant hybrid LLCs that collaboratively optimize for lifetime and performance. Specifically, we leverage data compression to utilize partially defective NVM cache entries, thereby improving the LLC hit rate. The key to our approach is to guide the insertion policy by both the reuse properties of the block and the size resulting from its compression. A block is inserted in NVM only if it is a read-reuse block or its compressed size is lower than a threshold. It will be inserted in SRAM if the block is a write-reuse or its compressed size is greater than the threshold. We use set-dueling to tune the compression threshold at runtime. This compression threshold provides a knob to control the NVM write rate and, together with a rule-based mechanism, allows balancing performance and lifetime.Overall, our evaluation shows that, with affordable hardware overheads, the proposed schemes can nearly reach the performance of an SRAM cache with the same associativity while improving lifetime by 17x compared to a hybrid NVM-unaware LLC. Our proposed scheme outperforms the state-of-the-art insertion policies by 9\% while achieving a comparative lifetime. The rule-based mechanism shows that by compromising, for instance, 1.1\% and 1.9\% performance, the NVM lifetime can be further increased by 28\% and 44\%, respectively.},
doi = {10.1109/HPCA56546.2023.10070968},
url = {https://doi.ieeecomputersociety.org/10.1109/HPCA56546.2023.10070968},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
month = mar,
year = {2023},
}Downloads
2302_Escuin_HPCA [PDF]
Related Paths
Permalink
- Johannes Hayeß, "Verifying the Rust Runtime of Lingua
Franca", Master's thesis, TU Dresden, March 2023. [Bibtex & Downloads]
Verifying the Rust Runtime of Lingua Franca
×Reference
Johannes Hayeß, "Verifying the Rust Runtime of Lingua Franca", Master's thesis, TU Dresden, March 2023.
Bibtex
@mastersthesis{Hayess-diploma23,
title={Verifying the Rust Runtime of Lingua
Franca},
author={Johannes Hayeß},
year={2023},
month=march,
school={TU Dresden},
}Downloads
2303_Hayess_MA [PDF]
Related Paths
Permalink
- Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023. [Bibtex & Downloads]
Formal Analysis of Camouflaged Reconfigurable Circuits
×Reference
Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023.
Bibtex
@inproceedings{mrt+23,
author = {M\"arcker, Steffen and Raitza, Michael and Rai, Shubham and Galderisi, Giulio and Mikolajick, Thomas and Trommer, Jens and Kumar, Akash},
title = {Formal Analysis of Camouflaged Reconfigurable Circuits},
year = {2023},
volume = {},
number = {},
pages = {1--4},
booktitle = {Proceedings 21st International NEWCAS Conference}
}Downloads
newcas23-camouflaging [PDF]
Related Paths
Permalink
2022
- Fazal Hameed, Jeronimo Castrillon, "BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 41, pp. 5288–5298, Dec 2022. [doi] [Bibtex & Downloads]
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture
×Reference
Fazal Hameed, Jeronimo Castrillon, "BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 41, pp. 5288–5298, Dec 2022. [doi]
Abstract
Racetrack memory (RTM) is a promising nonvolatile memory that provides multi-bit storage cells achieving a higher area and leakage energy efficiency compared to contemporary volatile and non-volatile memories. These features make RTM a potential candidate to be used as a Last-Level-Cache (LLC). One drawback of the multi-bit RTM cell is the serialized access to the stored data, resulting in a shift penalty to access a particular bit within the cell. This overhead is particularly critical for LLC tags, for which prior RTM designs place tags either in SRAM or in single-bit RTM cells. While this avoids shifting, these designs require large number of leaky cells incurring high energy consumption. To address this problem, this paper proposes an energy efficient RTM design called BlendCache that efficiently stores the tags in the leakage optimized multi-bit RTM cells. To reduce the RTM shift penalty of these cells, BlendCache exploits the spatial locality of programs by maximizing accesses to nearby locations in RTM. Employing 32-bit RTM cells for a single-core, BlendCache reduces the energy consumption by 20.8% and area by 15.2% compared to the state-of-the-art while its impact on performance is negligible. For a 4-core system, the energy improvement translates to 35.9% with 3% performance degradation.
Bibtex
@Article{hameed_tcad22,
author = {Fazal Hameed and Jeronimo Castrillon},
title = {{BlendCache}: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture},
doi = {10.1109/TCAD.2022.3161198},
issn = {0278-0070},
issue = {12},
pages = {5288--5298},
url = {https://ieeexplore.ieee.org/document/9739802},
volume = {41},
abstract = {Racetrack memory (RTM) is a promising nonvolatile memory that provides multi-bit storage cells achieving a higher area and leakage energy efficiency compared to contemporary volatile and non-volatile memories. These features make RTM a potential candidate to be used as a Last-Level-Cache (LLC). One drawback of the multi-bit RTM cell is the serialized access to the stored data, resulting in a shift penalty to access a particular bit within the cell. This overhead is particularly critical for LLC tags, for which prior RTM designs place tags either in SRAM or in single-bit RTM cells. While this avoids shifting, these designs require large number of leaky cells incurring high energy consumption. To address this problem, this paper proposes an energy efficient RTM design called BlendCache that efficiently stores the tags in the leakage optimized multi-bit RTM cells. To reduce the RTM shift penalty of these cells, BlendCache exploits the spatial locality of programs by maximizing accesses to nearby locations in RTM. Employing 32-bit RTM cells for a single-core, BlendCache reduces the energy consumption by 20.8\% and area by 15.2\% compared to the state-of-the-art while its impact on performance is negligible. For a 4-core system, the energy improvement translates to 35.9\% with 3\% performance degradation.},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)},
month = dec,
project = {tracesymm,cfaed},
year = {2022},
}Downloads
2204_Hameed_TCAD [PDF]
Related Paths
Permalink
- Asif Ali Khan, "Design and Code Optimization for Systems with Next-generation Racetrack Memories", PhD thesis, TU Dresden, 255 pp., Apr 2022. [Bibtex & Downloads]
Design and Code Optimization for Systems with Next-generation Racetrack Memories
×Reference
Asif Ali Khan, "Design and Code Optimization for Systems with Next-generation Racetrack Memories", PhD thesis, TU Dresden, 255 pp., Apr 2022.
Bibtex
@PhdThesis{Khan_PhD,
author = {Khan, Asif Ali},
institution = {TU Dresden},
title = {Design and Code Optimization for Systems with Next-generation Racetrack Memories},
pages = {255 pp.},
month = apr,
year = {2022},
url = {https://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa2-795738},
}Downloads
2204_Khan_PhD [PDF]
Related Paths
Permalink
2021
- Nesrine Khouzami, Friedrich Michel, Pietro Incardona, Jeronimo Castrillon, Ivo F. Sbalzarini, "Model-based Autotuning of Discretization Methods in Numerical Simulations of Partial Differential Equations", In Journal of Computational Science, vol. 57, pp. 1–11, Dec 2021. [doi] [Bibtex & Downloads]
Model-based Autotuning of Discretization Methods in Numerical Simulations of Partial Differential Equations
×Reference
Nesrine Khouzami, Friedrich Michel, Pietro Incardona, Jeronimo Castrillon, Ivo F. Sbalzarini, "Model-based Autotuning of Discretization Methods in Numerical Simulations of Partial Differential Equations", In Journal of Computational Science, vol. 57, pp. 1–11, Dec 2021. [doi]
Abstract
We present an autotuning approach for compile-time optimization of numerical discretization methods in simulations of partial differential equations. Our approach is based on data-driven regression of performance models for numerical methods. We use these models at compile time to automatically determine the parameters (e.g., resolution, time step size, etc.) of numerical simulations of continuum spatio-temporal models in order to optimize the tradeoff between simulation accuracy and runtime. The resulting autotuner is developed for the compiler of a Domain-Specific Language (DSL) for numerical simulations. The abstractions in the DSL enable the compiler to automatically determine the performance models and know which discretization parameters to tune. We demonstrate that this high-level approach can explore a large space of possible simulations, with simulation runtimes spanning multiple orders of magnitude. We evaluate our approach in two test cases: the linear diffusion equation and the nonlinear Gray-Scott reaction–diffusion equation. The results show that our model-based autotuner consistently finds configurations that outperform those found by state-of-the-art general-purpose autotuners. Specifically, our autotuner yields simulations that are on average 4.2x faster than those found by the best generic exploration algorithms, while using 16x less tuning time. Compared to manual tuning by a group of researchers with varying levels of expertise, the autotuner was slower than the best users by not more than a factor of 2, whereas it was able to significantly outperform half of them.
Bibtex
@Article{khouzami_jocs21,
author = {Nesrine Khouzami and Friedrich Michel and Pietro Incardona and Jeronimo Castrillon and Ivo F. Sbalzarini},
date = {2021-12},
title = {Model-based Autotuning of Discretization Methods in Numerical Simulations of Partial Differential Equations},
doi = {10.1016/j.jocs.2021.101489},
issn = {1877-7503},
pages = {1--11},
url = {https://www.sciencedirect.com/science/article/pii/S1877750321001563},
volume = {57},
abstract = {We present an autotuning approach for compile-time optimization of numerical discretization methods in simulations of partial differential equations. Our approach is based on data-driven regression of performance models for numerical methods. We use these models at compile time to automatically determine the parameters (e.g., resolution, time step size, etc.) of numerical simulations of continuum spatio-temporal models in order to optimize the tradeoff between simulation accuracy and runtime. The resulting autotuner is developed for the compiler of a Domain-Specific Language (DSL) for numerical simulations. The abstractions in the DSL enable the compiler to automatically determine the performance models and know which discretization parameters to tune. We demonstrate that this high-level approach can explore a large space of possible simulations, with simulation runtimes spanning multiple orders of magnitude. We evaluate our approach in two test cases: the linear diffusion equation and the nonlinear Gray-Scott reaction–diffusion equation. The results show that our model-based autotuner consistently finds configurations that outperform those found by state-of-the-art general-purpose autotuners. Specifically, our autotuner yields simulations that are on average 4.2x faster than those found by the best generic exploration algorithms, while using 16x less tuning time. Compared to manual tuning by a group of researchers with varying levels of expertise, the autotuner was slower than the best users by not more than a factor of 2, whereas it was able to significantly outperform half of them.},
journal = {Journal of Computational Science},
month = dec,
numpages = {15},
project = {openpme},
year = {2021},
}Downloads
2111_Khouzami_JOCS [PDF]
Related Paths
Permalink
- Joonas Iisakki Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jääskeläinen, "Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory", In IEEE Transactions on Computers, pp. 1-1, Oct 2021. [doi] [Bibtex & Downloads]
Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory
×Reference
Joonas Iisakki Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jääskeläinen, "Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory", In IEEE Transactions on Computers, pp. 1-1, Oct 2021. [doi]
Bibtex
@Article{multanen_toc21,
author = {Joonas Iisakki Multanen and Kari Hepola and Asif Ali Khan and Jeronimo Castrillon and Pekka J{\"a}{\"a}skel{\"a}inen},
title = {Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory},
doi = {10.1109/TC.2021.3117439},
number = {9},
pages = {2010--2021},
url = {https://ieeexplore.ieee.org/document/9557799},
volume = {71},
abstract = {As performance and energy-efficiency improvements from technology scaling are slowing down, new technologies are being researched in hopes of disrupting results. Domain wall memory (DWM) is an emerging non-volatile technology that promises extreme data density, fast access times and low power consumption. However, DWM access time depends on the memory location distance from access ports, requiring expensive shifting. This causes overheads on performance and energy consumption. In this article, we implement our previously proposed shift-reducing instruction memory placement (SHRIMP) on a RISC-V core in RTL, provide the first thorough evaluation of the control logic required for DWM and SHRIMP and evaluate the effects on system energy and energy-efficiency. SHRIMP reduces the number of shifts by 36\% on average compared to a linear placement in CHStone and Coremark benchmark suites when evaluated on the RISC-V processor system. The reduced shift amount leads to an average reduction of 14\% in cycle counts compared to the linear placement. When compared to an SRAM-based system, although increasing memory usage by 26\%, DWM with SHRIMP allows a 73\% reduction in memory energy and 42\% relative energy delay product. We estimate overall energy reductions of 14\%, 15\% and 19\% in three example embedded systems.},
journal = {IEEE Transactions on Computers},
month = oct,
year = {2021},
}Downloads
2110_Multanen_TOC [PDF]
Related Paths
Permalink
- Robert Khasanov, Julian Robledo, Christian Menard, Andr'es Goens, Jeronimo Castrillon, "Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks", In ACM Transactions on Embedded Computing Systems (TECS). Special issue of the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), Association for Computing Machinery, vol. 20, no. 5s, New York, NY, USA, Sep 2021. [doi] [Bibtex & Downloads]
Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks
×Reference
Robert Khasanov, Julian Robledo, Christian Menard, Andr'es Goens, Jeronimo Castrillon, "Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks", In ACM Transactions on Embedded Computing Systems (TECS). Special issue of the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), Association for Computing Machinery, vol. 20, no. 5s, New York, NY, USA, Sep 2021. [doi]
Abstract
Advancing telecommunication standards continuously push for larger bandwidths, lower latencies, and faster data rates. The receiver baseband unit not only has to deal with a huge number of users expecting connectivity but also with a high workload heterogeneity. As a consequence of the required flexibility, baseband processing has seen a trend towards software implementations in cloud Radio Access Networks (cRANs). The flexibility gained from software implementation comes at the price of impoverished energy efficiency. This paper addresses the trade-off between flexibility and efficiency by proposing a domain-specific hybrid mapping algorithm. Hybrid mapping is an established approach from the model-based design of embedded systems that allows us to retain flexibility while targeting heterogeneous hardware. Depending on the current workload, the runtime system selects the most energy-efficient mapping configuration without violating timing constraints. We leverage the structure of baseband processing, and refine the scheduling methodology, to enable efficient mapping of 100s of tasks at the millisecond granularity, improving upon state-of-the-art hybrid approaches. We validate our approach on an Odroid XU4 and virtual platforms with application-specific accelerators on an open-source prototype. On different LTE workloads, our hybrid approach shows significant improvements both at design time and at runtime. At design-time, mappings of similar quality to those obtained by state-of-the-art methods are generated around four orders of magnitude faster. At runtime, multi-application schedules are computed 37.7% faster than the state-of-the-art without compromising on the quality.
Bibtex
@Article{khasanov_cases21,
author = {Robert Khasanov and Julian Robledo and Christian Menard and Andrés Goens and Jeronimo Castrillon},
title = {Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks},
doi = {10.1145/3476991},
issn = {1539-9087},
number = {5s},
url = {https://doi.org/10.1145/3476991},
volume = {20},
abstract = {Advancing telecommunication standards continuously push for larger bandwidths, lower latencies, and faster data rates. The receiver baseband unit not only has to deal with a huge number of users expecting connectivity but also with a high workload heterogeneity. As a consequence of the required flexibility, baseband processing has seen a trend towards software implementations in cloud Radio Access Networks (cRANs). The flexibility gained from software implementation comes at the price of impoverished energy efficiency. This paper addresses the trade-off between flexibility and efficiency by proposing a domain-specific hybrid mapping algorithm. Hybrid mapping is an established approach from the model-based design of embedded systems that allows us to retain flexibility while targeting heterogeneous hardware. Depending on the current workload, the runtime system selects the most energy-efficient mapping configuration without violating timing constraints. We leverage the structure of baseband processing, and refine the scheduling methodology, to enable efficient mapping of 100s of tasks at the millisecond granularity, improving upon state-of-the-art hybrid approaches. We validate our approach on an Odroid XU4 and virtual platforms with application-specific accelerators on an open-source prototype. On different LTE workloads, our hybrid approach shows significant improvements both at design time and at runtime. At design-time, mappings of similar quality to those obtained by state-of-the-art methods are generated around four orders of magnitude faster. At runtime, multi-application schedules are computed 37.7% faster than the state-of-the-art without compromising on the quality.},
address = {New York, NY, USA},
articleno = {60},
issue_date = {October 2021},
journal = {ACM Transactions on Embedded Computing Systems (TECS). Special issue of the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES)},
location = {Virtual conference},
month = sep,
numpages = {26},
publisher = {Association for Computing Machinery},
year = {2021},
}Downloads
2110_Khasanov_CASES [PDF]
Related Paths
Permalink
- Adam Siemieniuk, Lorenzo Chelini, Asif Ali Khan, Jeronimo Castrillon, Andi Drebes, Henk Corporaal, Tobias Grosser, Martin Kong, "OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Press, vol. 41, no. 6, pp. 1674-1686, Aug 2021. [doi] [Bibtex & Downloads]
OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory
×Reference
Adam Siemieniuk, Lorenzo Chelini, Asif Ali Khan, Jeronimo Castrillon, Andi Drebes, Henk Corporaal, Tobias Grosser, Martin Kong, "OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Press, vol. 41, no. 6, pp. 1674-1686, Aug 2021. [doi]
Bibtex
@Article{khan_tcad21,
author = {Adam Siemieniuk and Lorenzo Chelini and Asif Ali Khan and Jeronimo Castrillon and Andi Drebes and Henk Corporaal and Tobias Grosser and Martin Kong},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
title = {{OCC}: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory},
month = aug,
volume={41},
number={6},
pages={1674--1686},
numpages = {12 pp},
doi = {10.1109/TCAD.2021.3101464},
issn = {1937-4151},
url = {https://ieeexplore.ieee.org/document/9502921},
publisher = {IEEE Press},
year = {2021},
abstract = {Memristive devices promise an alternative approach toward non-Von Neumann architectures, where specific computational tasks are performed within the memory devices. In the machine learning (ML) domain, crossbar arrays of resistive devices have shown great promise for ML inference, as they allow for hardware acceleration of matrix multiplications. But, to enable widespread adoption of these novel architectures, it is critical to have an automatic compilation flow as opposed to relying on a manual mapping of specific kernels on the crossbar arrays. We demonstrate the programmability of memristor-based accelerators using the new compiler design principle of multilevel rewriting, where a hierarchy of abstractions lowers programs level-by-level and perform code transformations at the most suitable abstraction. In particular, we develop a prototype compiler, which progressively lowers a mathematical notation for tensor operations arising in ML workloads, to fixed-function memristor-based hardware blocks.},
}Downloads
2107_Khan_TCAD [PDF]
Related Paths
Permalink
- Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] [Bibtex & Downloads]
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
×Reference
Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi]
Bibtex
@article{Nambi_2021,
doi = {10.1109/access.2021.3098730},
url = {https://doi.org/10.1109%2Faccess.2021.3098730},
year = 2021,
month = {July},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Suresh Nambi and Salim Ullah and Siva Satyendra Sahoo and Aditya Lohana and Farhad Merchant and Akash Kumar},
title = {{ExPAN}(N)D: Exploring Posits for Efficient Artificial Neural Network Design in {FPGA}-based Systems},
journal = {{IEEE} Access}
}Downloads
ExPANND_Exploring_Posits_for_Efficient_Artificial_Neural_Network_Design_in_FPGA-based_Systems [PDF]
Related Paths
Permalink
- Andr'es Goens, Jeronimo Castrillon, "Embeddings of Task Mappings to Multicore Systems", Proceedings of the 21st IEEE International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS), Springer-Verlag, pp. 161–176, Berlin, Heidelberg, Jul 2021. [doi] [Bibtex & Downloads]
Embeddings of Task Mappings to Multicore Systems
×Reference
Andr'es Goens, Jeronimo Castrillon, "Embeddings of Task Mappings to Multicore Systems", Proceedings of the 21st IEEE International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS), Springer-Verlag, pp. 161–176, Berlin, Heidelberg, Jul 2021. [doi]
Abstract
The problem of finding good mappings is central to designing and executing applications efficiently in embedded systems. In heterogeneous multicores, which are ubiquitous today, this problem yields an intractably large design space of possible mappings. Most methods explore this space using heuristics, many of which implicitly use geometric notions in mappings. In this paper we explore the geometry of the mapping problem explicitly, for finding embeddings of the mapping space that capture its structure. This allows us to formulate new mapping strategies by leveraging the geometry of the mapping space, as well as improving existing heuristics that do so implicitly. We evaluate our approach on a novel mapping heuristic based on gradient descent, as well as multiple existing meta-heuristics. For complex architectures, our methods improved the results of established exploration meta-heuristics by about an order of magnitude in average.
Bibtex
@InProceedings{goens_samos21,
author = {Andrés Goens and Jeronimo Castrillon},
booktitle = {Proceedings of the 21st IEEE International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS)},
date = {2021-07},
title = {Embeddings of Task Mappings to Multicore Systems},
doi = {10.1007/978-3-031-04580-6_11},
isbn = {978-3-031-04579-0},
location = {Samos, Greece},
organization = {IEEE},
pages = {161--176},
publisher = {Springer-Verlag},
url = {https://doi.org/10.1007/978-3-031-04580-6_11},
abstract = {The problem of finding good mappings is central to designing and executing applications efficiently in embedded systems. In heterogeneous multicores, which are ubiquitous today, this problem yields an intractably large design space of possible mappings. Most methods explore this space using heuristics, many of which implicitly use geometric notions in mappings. In this paper we explore the geometry of the mapping problem explicitly, for finding embeddings of the mapping space that capture its structure. This allows us to formulate new mapping strategies by leveraging the geometry of the mapping space, as well as improving existing heuristics that do so implicitly. We evaluate our approach on a novel mapping heuristic based on gradient descent, as well as multiple existing meta-heuristics. For complex architectures, our methods improved the results of established exploration meta-heuristics by about an order of magnitude in average.},
address = {Berlin, Heidelberg},
month = jul,
numpages = {16},
year = {2021},
}Downloads
2107_Goens_SAMOS [PDF]
Related Paths
Permalink
- Jeronimo Castrillon, "Domain specific languages to tame heterogeneous and emerging computing systems", In ACM SIGHPC conference Platform for Advanced Scientific Computing PASC'21 (keynote), Jul 2021. [Bibtex & Downloads]
Domain specific languages to tame heterogeneous and emerging computing systems
×Reference
Jeronimo Castrillon, "Domain specific languages to tame heterogeneous and emerging computing systems", In ACM SIGHPC conference Platform for Advanced Scientific Computing PASC'21 (keynote), Jul 2021.
Abstract
Programming heterogeneous computing systems is still a daunting task that will become even more challenging with the advent of emerging computer architectures. This complexity will make it harder to democratize high-performance computing, which already today highly relies on expert programmers to write efficient parallel code. This talk discusses domain specific languages (DSLs) as a promising avenue to tame heterogeneity for non-expert programmers. The high-level semantics in DSLs improves productivity while enabling coarser-grained optimization and safer code generation. Examples are provided from the domains of big-data, physics simulations and machine learning. The talk closes with insights on how compilers can leverage the high-level semantics of DSLs to optimize for emerging memory technologies.
Bibtex
@Misc{castrillon_pasc21,
author = {Castrillon, Jeronimo},
title = {Domain specific languages to tame heterogeneous and emerging computing systems},
howpublished = {ACM SIGHPC conference Platform for Advanced Scientific Computing PASC'21 (keynote)},
location = {Geneva (virtual), Switzerland},
abstract = {Programming heterogeneous computing systems is still a daunting task that will become even more challenging with the advent of emerging computer architectures. This complexity will make it harder to democratize high-performance computing, which already today highly relies on expert programmers to write efficient parallel code. This talk discusses domain specific languages (DSLs) as a promising avenue to tame heterogeneity for non-expert programmers. The high-level semantics in DSLs improves productivity while enabling coarser-grained optimization and safer code generation. Examples are provided from the domains of big-data, physics simulations and machine learning. The talk closes with insights on how compilers can leverage the high-level semantics of DSLs to optimize for emerging memory technologies.},
month = jul,
year = {2021},
}Downloads
210709_castrillon_PASC-sent [PDF]
Related Paths
Permalink
- Nesrine Khouzami, Lars Schütze, Pietro Incardona, Landfried Kraaz, Tina Subic, Jeronimo Castrillon, Ivo F. Sbalzarini, "The OpenPME Problem Solving Environment for Numerical Simulations", In Proceeding: International Conference on Computational Science (ICCS'21) (Paszynski, Maciej and Kranzlmüller, Dieter and Krzhizhanovskaya, Valeria V. and Dongarra, Jack J. and Sloot, Peter M. A.), Springer International Publishing, pp. 614–627, Cham, Jun 2021. [doi] [Bibtex & Downloads]
The OpenPME Problem Solving Environment for Numerical Simulations
×Reference
Nesrine Khouzami, Lars Schütze, Pietro Incardona, Landfried Kraaz, Tina Subic, Jeronimo Castrillon, Ivo F. Sbalzarini, "The OpenPME Problem Solving Environment for Numerical Simulations", In Proceeding: International Conference on Computational Science (ICCS'21) (Paszynski, Maciej and Kranzlmüller, Dieter and Krzhizhanovskaya, Valeria V. and Dongarra, Jack J. and Sloot, Peter M. A.), Springer International Publishing, pp. 614–627, Cham, Jun 2021. [doi]
Abstract
We introduce OpenPME, the Open Particle-Mesh Environment, a problem solving environment that provides a Domain Specific Language (DSL) for numerical simulations in scientific computing. It is built atop a domain metamodel that is general enough to cover the main types of numerical simulations: simulations using particles, meshes, and hybrid combinations of particles and meshes. Using model-to-model transformations, OpenPME generates code against the state-of-the-art C++ parallel computing library OpenFPM. This effectively lowers the programming barrier and enables users to implement scalable simulation codes for high-performance computing (HPC) systems using high-level abstractions. Plenty of recent research has shown that higher-level abstractions and problem solving environments are well suited to alleviate low-level implementation overhead. We demonstrate this for OpenPME and its compiler on three different test cases—particle-based, mesh-based, and hybrid particle-mesh—showing up to 7-fold reduction in the number of lines of code compared to a direct OpenFPM implementation in C++.
Bibtex
@InProceedings{khouzami_iccs21,
author = {Nesrine Khouzami and Lars Sch{\"u}tze and Pietro Incardona and Landfried Kraaz and Tina Subic and Jeronimo Castrillon and Ivo F. Sbalzarini},
booktitle = {International Conference on Computational Science (ICCS'21)},
title = {The OpenPME Problem Solving Environment for Numerical Simulations},
doi = {10.1007/978-3-030-77961-0_49},
editor = {Paszynski, Maciej and Kranzlm{\"u}ller, Dieter and Krzhizhanovskaya, Valeria V. and Dongarra, Jack J. and Sloot, Peter M. A.},
isbn = {978-3-030-77961-0},
location = {Krakow (virtual), Poland},
organization = {Springer},
pages = {614--627},
publisher = {Springer International Publishing},
url = {https://link.springer.com/chapter/10.1007%2F978-3-030-77961-0_49},
abstract = {We introduce OpenPME, the Open Particle-Mesh Environment, a problem solving environment that provides a Domain Specific Language (DSL) for numerical simulations in scientific computing. It is built atop a domain metamodel that is general enough to cover the main types of numerical simulations: simulations using particles, meshes, and hybrid combinations of particles and meshes. Using model-to-model transformations, OpenPME generates code against the state-of-the-art C++ parallel computing library OpenFPM. This effectively lowers the programming barrier and enables users to implement scalable simulation codes for high-performance computing (HPC) systems using high-level abstractions. Plenty of recent research has shown that higher-level abstractions and problem solving environments are well suited to alleviate low-level implementation overhead. We demonstrate this for OpenPME and its compiler on three different test cases---particle-based, mesh-based, and hybrid particle-mesh---showing up to 7-fold reduction in the number of lines of code compared to a direct OpenFPM implementation in C++.},
address = {Cham},
month = jun,
numpages = {14},
year = {2021},
}Downloads
2106_Khouzami_ICCS [PDF]
Related Paths
Permalink
- Andres Wilhelm Goens Jokisch, "Improving Model-Based Software Synthesis: A Focus on Mathematical Structures", PhD thesis, TU Dresden, 172 pp., May 2021. [Bibtex & Downloads]
Improving Model-Based Software Synthesis: A Focus on Mathematical Structures
×Reference
Andres Wilhelm Goens Jokisch, "Improving Model-Based Software Synthesis: A Focus on Mathematical Structures", PhD thesis, TU Dresden, 172 pp., May 2021.
Bibtex
@PhdThesis{goens_phd21,
author = {Goens Jokisch, Andres Wilhelm},
institution = {TU Dresden},
title = {Improving Model-Based Software Synthesis: A Focus on Mathematical Structures},
pages = {172 pp.},
month = may,
year = {2021},
url = {https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa2-748845},
}Downloads
2021_Goens_PhD [PDF]
Related Paths
Permalink
2020
- Asif Ali Khan, Hauke Mewes, Tobias Grosser, Torsten Hoefler, Jeronimo Castrillon, "Polyhedral Compilation for Racetrack Memories", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'20), IEEE Press, vol. 39, no. 11, pp. 3968–3980, Oct 2020. [doi] [Bibtex & Downloads]
Polyhedral Compilation for Racetrack Memories
×Reference
Asif Ali Khan, Hauke Mewes, Tobias Grosser, Torsten Hoefler, Jeronimo Castrillon, "Polyhedral Compilation for Racetrack Memories", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'20), IEEE Press, vol. 39, no. 11, pp. 3968–3980, Oct 2020. [doi]
Abstract
Traditional memory hierarchy designs, primarily based on SRAM and DRAM, become increasingly unsuitable to meet the performance, energy, bandwidth and area requirements of modern embedded and high-performance computer systems. Racetrack Memory (RTM), an emerging non-volatile memory technology, promises to meet these conflicting demands by offering simultaneously high speed, higher density, and non-volatility. RTM provides these efficiency gains by not providing immediate access to all storage locations, but by instead storing data sequentially in the equivalent to nanoscale tapes called tracks. Before any data can be accessed, explicit shift operations must be issued that cost energy and increase access latency. The result is a fundamental change in memory performance behavior: the address distance between subsequent memory accesses now has a linear effect on memory performance. While there are first techniques to optimize programs for linear-latency memories such as RTM, existing automatic solutions treat only scalar memory accesses. This work presents the first automatic compilation framework that optimizes static loop programs over arrays for linear-latency memories. We extend the polyhedral compilation framework Polly to generate code that maximizes accesses to the same or consecutive locations, thereby minimizing the number of shifts. Our experimental results show that the optimized code incurs up to 85% fewer shifts (average 41%), improving both performance and energy consumption by an average of 17.9% and 39.8%, respectively. Our results show that automatic techniques make it possible to effectively program linear-latency memory architectures such as RTM.
Bibtex
@Article{khan_cases20,
author = {Asif Ali Khan and Hauke Mewes and Tobias Grosser and Torsten Hoefler and Jeronimo Castrillon},
title = {Polyhedral Compilation for Racetrack Memories},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'20)},
year = {2020},
series = {CASES ’20},
month = oct,
doi = {10.1109/TCAD.2020.3012266},
url = {https://ieeexplore.ieee.org/document/9216560},
volume={39},
number={11},
pages={3968--3980},
issn = {1937-4151},
issn = {1937-4151},
abstract = {Traditional memory hierarchy designs, primarily based on SRAM and DRAM, become increasingly unsuitable to meet the performance, energy, bandwidth and area requirements of modern embedded and high-performance computer systems. Racetrack Memory (RTM), an emerging non-volatile memory technology, promises to meet these conflicting demands by offering simultaneously high speed, higher density, and non-volatility. RTM provides these efficiency gains by not providing immediate access to all storage locations, but by instead storing data sequentially in the equivalent to nanoscale tapes called tracks. Before any data can be accessed, explicit shift operations must be issued that cost energy and increase access latency. The result is a fundamental change in memory performance behavior: the address distance between subsequent memory accesses now has a linear effect on memory performance. While there are first techniques to optimize programs for linear-latency memories such as RTM, existing automatic solutions treat only scalar memory accesses. This work presents the first automatic compilation framework that optimizes static loop programs over arrays for linear-latency memories. We extend the polyhedral compilation framework Polly to generate code that maximizes accesses to the same or consecutive locations, thereby minimizing the number of shifts. Our experimental results show that the optimized code incurs up to 85\% fewer shifts (average 41\%), improving both performance and energy consumption by an average of 17.9\% and 39.8\%, respectively. Our results show that automatic techniques make it possible to effectively program linear-latency memory architectures such as RTM.},
booktitle = {Proceedings of the 2020 International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES)},
location = {Virtual conference},
numpages = {12},
publisher = {IEEE Press},
}Downloads
2009_Khan_CASES [PDF]
Related Paths
Permalink
- Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Improving the Performance of Block-based DRAM Caches via Tag-Data Decoupling", In IEEE Transactions on Computers, vol. 70, no. 11, pp. 1914-1927, Oct 2020. [doi] [Bibtex & Downloads]
Improving the Performance of Block-based DRAM Caches via Tag-Data Decoupling
×Reference
Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Improving the Performance of Block-based DRAM Caches via Tag-Data Decoupling", In IEEE Transactions on Computers, vol. 70, no. 11, pp. 1914-1927, Oct 2020. [doi]
Abstract
In-package DRAM-based Last-Level-Caches (LLCs) that cache data in small chunks (i.e., blocks) are promising for improving system performance due to their efficient main memory bandwidth utilization. However, in these high-capacity DRAM caches, managing metadata (i.e., tags) at low cost is challenging. Storing the tags in SRAM has the advantage of quick tag access but is impractical due to a large area overhead. Storing the tags in DRAM reduces the area overhead but incurs tag serialization latency for an associative LLC design, which is inevitable for achieving high cache hit rate. To address the area and latency overhead problem, we propose a block- based DRAM LLC design that decouples tag and data into two regions in DRAM. Our design stores the tags in a latency-optimized DRAM region as the tags are accessed more often than the data. In contrast, we optimize the data region for area efficiency and map spatially-adjacent cache blocks to the same DRAM row to exploit spatial locality. Our design mitigates the tag serialization latency of existing associative DRAM LLCs via selective in-DRAM tag comparison, which overlaps the latency of tag and data accesses. This efficiently enables LLC bypassing via a novel DRAM Absence Table (DAT) that not only provides fast LLC miss detection but also reduces in-package bandwidth requirements. Our evaluation using SPEC2006 benchmarks shows that our tag-data decoupled LLC improves system performance by 11.7% compared to a state-of-the-art direct-mapped LLC design and by 7.2% compared to an existing associative LLC design.
Bibtex
@Article{hameed_tc20,
author = {Fazal Hameed and Asif Ali Khan and Jeronimo Castrillon},
title = {Improving the Performance of Block-based DRAM Caches via Tag-Data Decoupling},
journal = {IEEE Transactions on Computers},
year = {2020},
month = oct,
abstract = {In-package DRAM-based Last-Level-Caches (LLCs) that cache data in small chunks (i.e., blocks) are promising for improving system performance due to their efficient main memory bandwidth utilization. However, in these high-capacity DRAM caches, managing metadata (i.e., tags) at low cost is challenging. Storing the tags in SRAM has the advantage of quick tag access but is impractical due to a large area overhead. Storing the tags in DRAM reduces the area overhead but incurs tag serialization latency for an associative LLC design, which is inevitable for achieving high cache hit rate. To address the area and latency overhead problem, we propose a block- based DRAM LLC design that decouples tag and data into two regions in DRAM. Our design stores the tags in a latency-optimized DRAM region as the tags are accessed more often than the data. In contrast, we optimize the data region for area efficiency and map spatially-adjacent cache blocks to the same DRAM row to exploit spatial locality. Our design mitigates the tag serialization latency of existing associative DRAM LLCs via selective in-DRAM tag comparison, which overlaps the latency of tag and data accesses. This efficiently enables LLC bypassing via a novel DRAM Absence Table (DAT) that not only provides fast LLC miss detection but also reduces in-package bandwidth requirements. Our evaluation using SPEC2006 benchmarks shows that our tag-data decoupled LLC improves system performance by 11.7\% compared to a state-of-the-art direct-mapped LLC design and by 7.2\% compared to an existing associative LLC design.},
doi = {10.1109/TC.2020.3029615},
url = {https://ieeexplore.ieee.org/document/9220805},
issn = {0018-9340},
numpages = {14},
volume={70},
number={11},
pages={1914-1927},
}Downloads
2010_Hameed_TC [PDF]
Related Paths
Permalink
- Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories", In ACM Transactions on Embedded Computing Systems (TECS), Association for Computing Machinery, vol. 19, no. 6, New York, NY, USA, Sep 2020. [doi] [Bibtex & Downloads]
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories
×Reference
Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories", In ACM Transactions on Embedded Computing Systems (TECS), Association for Computing Machinery, vol. 19, no. 6, New York, NY, USA, Sep 2020. [doi]
Abstract
Tensor contraction is a fundamental operation in many algorithms with a plethora of applications ranging from quantum chemistry over fluid dynamics and image processing to machine learning. The performance of tensor computations critically depends on the efficient utilization of on-chip/off-chip memories. In the context of low-power embedded devices, efficient management of the memory space becomes even more crucial, in order to meet energy constraints. This work aims at investigating strategies for performance- and energy-efficient tensor contractions on embedded systems, using racetrack memory (RTM)-based scratch-pad memory (SPM) and DRAM-based off-chip memory. Compiler optimizations such as the loop access order and data layout transformations paired with architectural optimizations such as prefetching and preshifting are employed to reduce the shifting overhead in RTMs. Optimizations for off-chip memory such as memory access order, data mapping and the choice of a suitable memory access granularity are employed to reduce the contention in the off-chip memory. Experimental results demonstrate that the proposed optimizations improve the SPM performance and energy consumption by 32% and 73% respectively compared to an iso-capacity SRAM. The overall DRAM dynamic energy consumption improvements due to memory optimizations amount to 80%.
Bibtex
@Article{khan_tecs20,
author = {Asif Ali Khan and Norman A. Rink and Fazal Hameed and Jeronimo Castrillon},
title = {Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories},
journal = {ACM Transactions on Embedded Computing Systems (TECS)},
year = {2020},
month = sep,
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {19},
number = {6},
issn = {1539-9087},
url = {https://doi.org/10.1145/3396235},
doi = {10.1145/3396235},
articleno = {44},
numpages = {26},
abstract = {Tensor contraction is a fundamental operation in many algorithms with a plethora of applications ranging from quantum chemistry over fluid dynamics and image processing to machine learning. The performance of tensor computations critically depends on the efficient utilization of on-chip/off-chip memories. In the context of low-power embedded devices, efficient management of the memory space becomes even more crucial, in order to meet energy constraints. This work aims at investigating strategies for performance- and energy-efficient tensor contractions on embedded systems, using racetrack memory (RTM)-based scratch-pad memory (SPM) and DRAM-based off-chip memory. Compiler optimizations such as the loop access order and data layout transformations paired with architectural optimizations such as prefetching and preshifting are employed to reduce the shifting overhead in RTMs. Optimizations for off-chip memory such as memory access order, data mapping and the choice of a suitable memory access granularity are employed to reduce the contention in the off-chip memory. Experimental results demonstrate that the proposed optimizations improve the SPM performance and energy consumption by 32\% and 73\% respectively compared to an iso-capacity SRAM. The overall DRAM dynamic energy consumption improvements due to memory optimizations amount to 80\%.},
}Downloads
2009_Khan_TECS [PDF]
Related Paths
Permalink
- Friedrich Michel, "Multi-Objective Autotuning Targeting a Domain Specific Language for Particle Simulations", Master's thesis, TU Dresden, May 2020. [Bibtex & Downloads]
Multi-Objective Autotuning Targeting a Domain Specific Language for Particle Simulations
×Reference
Friedrich Michel, "Multi-Objective Autotuning Targeting a Domain Specific Language for Particle Simulations", Master's thesis, TU Dresden, May 2020.
Bibtex
@mastersthesis{Michel-master20,
title={Multi-Objective Autotuning Targeting a Domain Specific Language for Particle Simulations},
author={Friedrich Michel},
year={2020},
month=may,
school={TU Dresden},
}Downloads
2006_Michel_MA [PDF]
Related Paths
Permalink
- Christian Menard, Andrés Goens, Marten Lohstroh, Jeronimo Castrillon, "Achieving Determinism in Adaptive AUTOSAR", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 822–827, Mar 2020. (Best paper award candidate A-Track, Video Presentation) [doi] [Bibtex & Downloads]
Achieving Determinism in Adaptive AUTOSAR
×Reference
Christian Menard, Andrés Goens, Marten Lohstroh, Jeronimo Castrillon, "Achieving Determinism in Adaptive AUTOSAR", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 822–827, Mar 2020. (Best paper award candidate A-Track, Video Presentation) [doi]
Abstract
AUTOSAR AP is an emerging industry standard that tackles the challenges of modern automotive software design, but does not provide adequate mechanisms to enforce deterministic execution. This poses profound challenges to testing and maintenance of the application software, which is particularly problematic for safety-critical applications. In this paper, we analyze the problem of nondeterminism in AP and propose a framework for the design of deterministic automotive software that transparently integrates with the AP communication mechanisms. We illustrate our approach in a case study based on the brake assistant demonstrator application that is provided by the AUTOSAR consortium. We show that the original implementation is nondeterministic and discuss a deterministic solution based on our framework.
Bibtex
@InProceedings{menard_date20,
author = {Christian Menard and Andr{\'e}s Goens and Marten Lohstroh and Jeronimo Castrillon},
title = {Achieving Determinism in Adaptive AUTOSAR},
booktitle = {Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE)},
year = {2020},
series = {DATE '20},
month = mar,
publisher = {IEEE},
location = {Grenoble, France},
abstract = {AUTOSAR AP is an emerging industry standard that tackles the challenges of modern automotive software design, but does not provide adequate mechanisms to enforce deterministic execution. This poses profound challenges to testing and maintenance of the application software, which is particularly problematic for safety-critical applications. In this paper, we analyze the problem of nondeterminism in AP and propose a framework for the design of deterministic automotive software that transparently integrates with the AP communication mechanisms. We illustrate our approach in a case study based on the brake assistant demonstrator application that is provided by the AUTOSAR consortium. We show that the original implementation is nondeterministic and discuss a deterministic solution based on our framework.},
isbn = {978-3-9819263-4-7},
pages = {822--827},
doi = {10.23919/DATE48585.2020.9116430},
url = {https://ieeexplore.ieee.org/abstract/document/9116430},
}Downloads
2003_Menard_DATE [PDF]
Related Paths
Permalink
- Robert Khasanov, Jeronimo Castrillon, "Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 909–914, Mar 2020. (Best paper award candidate E-Track, Video Presentation) [doi] [Bibtex & Downloads]
Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping
×Reference
Robert Khasanov, Jeronimo Castrillon, "Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 909–914, Mar 2020. (Best paper award candidate E-Track, Video Presentation) [doi]
Abstract
Modern embedded computing platforms consist of a high amount of heterogeneous resources, which allows executing multiple applications on a single device. The number of running application on the system varies with time and so does the amount of available resources. This has considerably increased the complexity of analysis and optimization algorithms for runtime mapping of firm real-time applications. To reduce the runtime overhead, researchers have proposed to pre-compute partial mappings at compile time and have the runtime efficiently compute the final mapping. However, most existing solutions only compute a fixed mapping for a given set of running applications, and the mapping is defined for the entire duration of the workload execution. In this work we allow applications to adapt to the amount of available resources by using mapping segments. This way, applications may switch between different configurations with varied degree of parallelism. We present a runtime manager for firm real-time applications that generates such mapping segments based on partial solutions and aims at minimizing the overall energy consumption without deadline violations. The proposed algorithm outperforms the state-of-the-art approaches on the overall energy consumption by up to 13% while incurring an order of magnitude less scheduling overhead.
Bibtex
@InProceedings{khasanov_date20,
author = {Robert Khasanov and Jeronimo Castrillon},
title = {Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping},
booktitle = {Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE)},
year = {2020},
series = {DATE '20},
month = mar,
publisher = {IEEE},
location = {Grenoble, France},
isbn = {978-3-9819263-4-7},
pages = {909--914},
doi = {10.23919/DATE48585.2020.9116381},
url = {https://ieeexplore.ieee.org/document/9116381},
abstract = {Modern embedded computing platforms consist of a high amount of heterogeneous resources, which allows executing multiple applications on a single device. The number of running application on the system varies with time and so does the amount of available resources. This has considerably increased the complexity of analysis and optimization algorithms for runtime mapping of firm real-time applications. To reduce the runtime overhead, researchers have proposed to pre-compute partial mappings at compile time and have the runtime efficiently compute the final mapping. However, most existing solutions only compute a fixed mapping for a given set of running applications, and the mapping is defined for the entire duration of the workload execution. In this work we allow applications to adapt to the amount of available resources by using mapping segments. This way, applications may switch between different configurations with varied degree of parallelism. We present a runtime manager for firm real-time applications that generates such mapping segments based on partial solutions and aims at minimizing the overall energy consumption without deadline violations. The proposed algorithm outperforms the state-of-the-art approaches on the overall energy consumption by up to 13% while incurring an order of magnitude less scheduling overhead.},
}Downloads
2003_Khasanov_DATE [PDF]
Related Paths
Permalink
- Asif Ali Khan, Andrés Goens, Fazal Hameed, Jeronimo Castrillon, "Generalized Data Placement Strategies for Racetrack Memories", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 1502–1507, Mar 2020. (Video Presentation) [doi] [Bibtex & Downloads]
Generalized Data Placement Strategies for Racetrack Memories
×Reference
Asif Ali Khan, Andrés Goens, Fazal Hameed, Jeronimo Castrillon, "Generalized Data Placement Strategies for Racetrack Memories", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 1502–1507, Mar 2020. (Video Presentation) [doi]
Abstract
Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate shift operations in RTMs hinder their applicability to replace low-latency on-chip memories. Recent research has demonstrated that intelligent placement of memory objects in RTMs can significantly reduce the amount of shifts with no hardware overhead, albeit for specific system setups. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. In this paper we look at generalized data placement mechanisms that improve upon existing ones by taking into account the underlying memory architecture and the timing and liveliness information of memory objects. We propose a novel heuristic and a formulation using genetic algorithms that optimize key performance parameters. We show that, on average, our generalized approach improves the number of shifts, performance and energy consumption by 4.3x, 46% and 55% respectively compared to the state-of-the-art.
Bibtex
@InProceedings{khan_date20,
author = {Asif Ali Khan and Andr{\'e}s Goens and Fazal Hameed and Jeronimo Castrillon},
title = {Generalized Data Placement Strategies for Racetrack Memories},
booktitle = {Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE)},
year = {2020},
series = {DATE '20},
publisher = {IEEE},
location = {Grenoble, France},
month = mar,
isbn = {978-3-9819263-4-7},
pages = {1502--1507},
doi = {10.23919/DATE48585.2020.9116245},
url = {https://ieeexplore.ieee.org/document/9116245},
abstract = {Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate shift operations in RTMs hinder their applicability to replace low-latency on-chip memories. Recent research has demonstrated that intelligent placement of memory objects in RTMs can significantly reduce the amount of shifts with no hardware overhead, albeit for specific system setups. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. In this paper we look at generalized data placement mechanisms that improve upon existing ones by taking into account the underlying memory architecture and the timing and liveliness information of memory objects. We propose a novel heuristic and a formulation using genetic algorithms that optimize key performance parameters. We show that, on average, our generalized approach improves the number of shifts, performance and energy consumption by 4.3x, 46% and 55% respectively compared to the state-of-the-art.},
}Downloads
2003_Khan_DATE [PDF]
Related Paths
Permalink
- Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jeronimo Castrillon, Stuart S. P. Parkin, "Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade", In Proceedings of the IEEE, vol. 108, no. 8, pp. 1303-1321, Mar 2020. [doi] [Bibtex & Downloads]
Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade
×Reference
Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jeronimo Castrillon, Stuart S. P. Parkin, "Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade", In Proceedings of the IEEE, vol. 108, no. 8, pp. 1303-1321, Mar 2020. [doi]
Bibtex
@Article{khan_pieee20,
author = {Robin Bl{\"a}sing and Asif Ali Khan and Panagiotis Ch. Filippou and Chirag Garg and Fazal Hameed and Jeronimo Castrillon and Stuart S. P. Parkin},
title = {Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade},
journal = {Proceedings of the IEEE},
year = {2020},
month = mar,
volume={108},
number={8},
pages={1303-1321},
doi = {10.1109/JPROC.2020.2975719},
url = {https://ieeexplore.ieee.org/document/9045991},
}Downloads
2003_Khan_JPROC [PDF]
Related Paths
Permalink
- Marten Lohstroh, Íñigo Íncer Romero, Andrés Goens, Patricia Derler, Jeronimo Castrillon, Edward A. Lee, Alberto Sangiovanni-Vincentelli, "Reactors: A Deterministic Model for Composable Reactive Systems", Cyber Physical Systems. Model-Based Design – Proceedings of the 9th Workshop on Design, Modeling and Evaluation of Cyber Physical Systems (CyPhy 2019) and the Workshop on Embedded and Cyber-Physical Systems Education (WESE 2019) (Chamberlain, Roger and Edin Grimheden, Martin and Taha, Walid), Springer International Publishing, pp. 59–85, Cham, Feb 2020. [doi] [Bibtex & Downloads]
Reactors: A Deterministic Model for Composable Reactive Systems
×Reference
Marten Lohstroh, Íñigo Íncer Romero, Andrés Goens, Patricia Derler, Jeronimo Castrillon, Edward A. Lee, Alberto Sangiovanni-Vincentelli, "Reactors: A Deterministic Model for Composable Reactive Systems", Cyber Physical Systems. Model-Based Design – Proceedings of the 9th Workshop on Design, Modeling and Evaluation of Cyber Physical Systems (CyPhy 2019) and the Workshop on Embedded and Cyber-Physical Systems Education (WESE 2019) (Chamberlain, Roger and Edin Grimheden, Martin and Taha, Walid), Springer International Publishing, pp. 59–85, Cham, Feb 2020. [doi]
Abstract
This paper describes a component-based concurrent model of computation for reactive systems. The components in this model, featuring ports and hierarchy, are called reactors. The model leverages a semantic notion of time, an event scheduler, and a synchronous-reactive style of communication to achieve determinism. Reactors enable a programming model that ensures determinism, unless explicitly abandoned by the programmer. We show how the coordination of reactors can safely and transparently exploit parallelism, both in shared-memory and distributed systems.
Bibtex
@InProceedings{Lohstroh_cyphy19,
author = {Marten Lohstroh and {\'I}{\~n}igo {\'I}ncer Romero and Andr\'{e}s Goens and Patricia Derler and Jeronimo Castrillon and Edward A. Lee and Alberto Sangiovanni-Vincentelli},
title = {Reactors: A Deterministic Model for Composable Reactive Systems},
editor= {Chamberlain, Roger and Edin Grimheden, Martin and Taha, Walid},
booktitle={Cyber Physical Systems. Model-Based Design -- Proceedings of the 9th Workshop on Design, Modeling and Evaluation of Cyber Physical Systems (CyPhy 2019) and the Workshop on Embedded and Cyber-Physical Systems Education (WESE 2019)},
year = {2020},
location = {New York City, NY, USA},
month = feb,
publisher={Springer International Publishing},
address={Cham},
pages={59--85},
abstract={This paper describes a component-based concurrent model of computation for reactive systems. The components in this model, featuring ports and hierarchy, are called reactors. The model leverages a semantic notion of time, an event scheduler, and a synchronous-reactive style of communication to achieve determinism. Reactors enable a programming model that ensures determinism, unless explicitly abandoned by the programmer. We show how the coordination of reactors can safely and transparently exploit parallelism, both in shared-memory and distributed systems.},
isbn={978-3-030-41131-2},
url = {https://link.springer.com/chapter/10.1007/978-3-030-41131-2_4},
doi = {10.1007/978-3-030-41131-2_4},
numpages = {27pp},
}Downloads
1910_Lohstroh_CyPhy [PDF]
Related Paths
Permalink
2019
- Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jeronimo Castrillon, "ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0", In ACM Transactions on Architecture and Code Optimization (TACO), ACM, vol. 16, no. 4, pp. 56:1–56:23, New York, NY, USA, Dec 2019. [doi] [Bibtex & Downloads]
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0
×Reference
Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jeronimo Castrillon, "ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0", In ACM Transactions on Architecture and Code Optimization (TACO), ACM, vol. 16, no. 4, pp. 56:1–56:23, New York, NY, USA, Dec 2019. [doi]
Abstract
Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This paper presents data placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%.
Bibtex
@Article{khan_taco19,
author = {Asif Ali Khan and Fazal Hameed and Robin Bl{\"a}sing and Stuart S. P. Parkin and Jeronimo Castrillon},
title = {ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0},
journal = {ACM Transactions on Architecture and Code Optimization (TACO)},
issue_date = {December 2019},
volume = {16},
number = {4},
month = dec,
year = {2019},
issn = {1544-3566},
pages = {56:1--56:23},
articleno = {56},
numpages = {23},
url = {http://doi.acm.org/10.1145/3372489},
doi = {10.1145/3372489},
acmid = {3372489},
publisher = {ACM},
address = {New York, NY, USA},
abstract = {Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This paper presents data placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5\%, outperforming the state of the art by up to 16.1\%.},
}Downloads
1912_Khan_TACO [PDF]
Related Paths
Permalink
- Sebastian Ertel, "Towards Implicit Parallel Programming for Systems", PhD thesis, TU Dresden, 121pp, Dec 2019. [Bibtex & Downloads]
Towards Implicit Parallel Programming for Systems
×Reference
Sebastian Ertel, "Towards Implicit Parallel Programming for Systems", PhD thesis, TU Dresden, 121pp, Dec 2019.
Bibtex
@PhdThesis{ertel19phd,
author = {Sebastian Ertel},
title = {Towards Implicit Parallel Programming for Systems},
year = {2019},
month = dec,
pages = {121pp},
school = {TU Dresden},
location = {Dresden, Germany},
url = {https://tud.qucosa.de/api/qucosa%3A36874/attachment/ATT-0/},
}Downloads
1912_Ertel_PhD [PDF]
Related Paths
Permalink
- Fazal Hameed, Jeronimo Castrillon, "A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy and Endurance Enhancement", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 27, no. 10, pp. 2375-2386, Oct 2019. [doi] [Bibtex & Downloads]
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy and Endurance Enhancement
×Reference
Fazal Hameed, Jeronimo Castrillon, "A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy and Endurance Enhancement", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 27, no. 10, pp. 2375-2386, Oct 2019. [doi]
Abstract
High capacity L4 architectures as Last-Level-Cache (LLC) have been recently introduced between L3-SRAM and off-chip memory. These LLC architectures have either employed DRAM or Spin-Transfer-Torque (STT-RAM) memory technologies. It is a known fact that DRAM LLCs feature a higher energy consumption while STT-RAM LLCs feature a lower write endurance compared to their counterparts. This paper proposes an efficient hybrid DRAM/STT-RAM LLC architecture that exploits the best characteristics offered by the individual memory technologies while mitigating their drawbacks. More precisely, we introduce a novel mechanism for the storage and management of the hybrid LLC tags, and a proactive L3-SRAM writeback policy that combines multiple dirty blocks that are mapped to the same LLC row. Our hybrid architecture reduces LLC interference by having less writeback accesses and row fetches. The endurance is improved by reducing the number of STT-RAM block writes. We show that our LLC architecture reduces the total number of STT-RAM block writes by 78% and improves the average performance by 13% compared to a recently proposed STT- RAM LLC. Compared to the state-of-the-art DRAM LLC, we report an average energy and performance improvement of 24% and 17.1% respectively.
Bibtex
@Article{hameed_tvlsi19,
author = {Fazal Hameed and Jeronimo Castrillon},
title = {A Novel Hybrid {DRAM}/{STT-RAM} {L}ast-{L}evel-{C}ache Architecture for Performance, Energy and Endurance Enhancement},
journal = {IEEE Transactions on Very Large Scale Integration Systems (TVLSI)},
year = {2019},
month = oct,
abstract = {High capacity L4 architectures as Last-Level-Cache (LLC) have been recently introduced between L3-SRAM and off-chip memory. These LLC architectures have either employed DRAM or Spin-Transfer-Torque (STT-RAM) memory technologies. It is a known fact that DRAM LLCs feature a higher energy consumption while STT-RAM LLCs feature a lower write endurance compared to their counterparts. This paper proposes an efficient hybrid DRAM/STT-RAM LLC architecture that exploits the best characteristics offered by the individual memory technologies while mitigating their drawbacks. More precisely, we introduce a novel mechanism for the storage and management of the hybrid LLC tags, and a proactive L3-SRAM writeback policy that combines multiple dirty blocks that are mapped to the same LLC row. Our hybrid architecture reduces LLC interference by having less writeback accesses and row fetches. The endurance is improved by reducing the number of STT-RAM block writes. We show that our LLC architecture reduces the total number of STT-RAM block writes by 78\% and improves the average performance by 13\% compared to a recently proposed STT- RAM LLC. Compared to the state-of-the-art DRAM LLC, we report an average energy and performance improvement of 24\% and 17.1\% respectively.},
volume = {27},
number = {10},
pages = {2375-2386},
numpages = {12pp},
doi={10.1109/TVLSI.2019.2918385},
url = {https://ieeexplore.ieee.org/document/8734763},
}Downloads
1905_Hameed_TVLSI [PDF]
Related Paths
Permalink
- Jeronimo Castrillon, "Dataflow and higher level abstractions for parallel programming", In CPS Summer School 2019: Designing Cyber-Physical Systems - From concepts to implementation (keynote), Sep 2019. [Bibtex & Downloads]
Dataflow and higher level abstractions for parallel programming
×Reference
Jeronimo Castrillon, "Dataflow and higher level abstractions for parallel programming", In CPS Summer School 2019: Designing Cyber-Physical Systems - From concepts to implementation (keynote), Sep 2019.
Abstract
Computing systems continue to increase in complexity, today including multiple cores, complex memory hierarchies and domain-specific accelerators, and soon with components built with emerging hardware technologies. This complexity calls for advances in a variety of domains, like programming and modeling languages, models of hardware, system simulators, design exploration methodologies and hardware architectures. From the standpoint of programming languages and compilers, this lecture discusses the challenges in mainstream sequential programming to motivate higher-level abstractions. It then provides an introduction to dataflow programming methodologies as a promising solution for embedded applications. We will review the fundamentals of dataflow models of computation, basic programming methodologies and look at current research to account for the adaptivity that new applications require, especially in the context of cyber physical systems. The lecture closes with an outlook on higher level programming abstractions and challenges posed by emerging computing architectures.
Bibtex
@Misc{castrillon_cpss19,
author = {Castrillon, Jeronimo},
title = {Dataflow and higher level abstractions for parallel programming},
howpublished = {CPS Summer School 2019: {Designing Cyber-Physical Systems - From concepts to implementation (keynote)}},
month = sep,
year = {2019},
abstract = {Computing systems continue to increase in complexity, today including multiple cores, complex memory hierarchies and domain-specific accelerators, and soon with components built with emerging hardware technologies. This complexity calls for advances in a variety of domains, like programming and modeling languages, models of hardware, system simulators, design exploration methodologies and hardware architectures. From the standpoint of programming languages and compilers, this lecture discusses the challenges in mainstream sequential programming to motivate higher-level abstractions. It then provides an introduction to dataflow programming methodologies as a promising solution for embedded applications. We will review the fundamentals of dataflow models of computation, basic programming methodologies and look at current research to account for the adaptivity that new applications require, especially in the context of cyber physical systems. The lecture closes with an outlook on higher level programming abstractions and challenges posed by emerging computing architectures.},
keywords = {invitedtalk},
location = {Alghero, Sardinia, Italy},
project = {cfaed, haec},
url = {http://www.cpsschool.eu/dataflow-and-higher-level-abstractions-for-parallel-programming/}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Ertel, Justus Adam, Norman A. Rink, Andrés Goens, Jeronimo Castrillon, "STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism", Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell, ACM, pp. 146–161, New York, NY, USA, Aug 2019. [doi] [Bibtex & Downloads]
STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism
×Reference
Sebastian Ertel, Justus Adam, Norman A. Rink, Andrés Goens, Jeronimo Castrillon, "STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism", Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell, ACM, pp. 146–161, New York, NY, USA, Aug 2019. [doi]
Abstract
Dataflow execution models are used to build highly scalable parallel systems. A programming model that targets parallel dataflow execution must answer the following question: How can parallelism between two dependent nodes in a dataflow graph be exploited? This is difficult when the dataflow language or programming model is implemented by a monad, as is common in the functional community, since expressing dependence between nodes by a monadic bind suggests sequential execution.
Even in monadic constructs that explicitly separate state from computation, problems arise due to the need to reason about opaquely defined state. Specifically, when abstractions of the chosen programming model do not enable adequate reasoning about state, it is difficult to detect parallelism between composed stateful computations.
In this paper, we propose a programming model that enables the composition of stateful computations and still exposes opportunities for parallelization. We also introduce smap, a higher-order function that can exploit parallelism in stateful computations. We present an implementation of our programming model and smap in Haskell and show that basic concepts from functional reactive programming can be built on top of our programming model with little effort. We compare these implementations to a state-of-the-art approach using monad-par and LVars to expose parallelism explicitly and reach the same level of performance, showing that our programming model successfully extracts parallelism that is present in an algorithm. Further evaluation shows that smap is expressive enough to implement parallel reductions and our programming model resolves short-comings of the stream-based programming model for current state-of-the-art big data processing systems.Bibtex
@InProceedings{ertel_haskell19,
author = {Ertel, Sebastian and Adam, Justus and Rink, Norman A. and Goens, Andr{\'e}s and Castrillon, Jeronimo},
title = {{STCLang}: State Thread Composition as a Foundation for Monadic Dataflow Parallelism},
booktitle = {Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell},
year = {2019},
series = {Haskell 2019},
pages = {146--161},
address = {New York, NY, USA},
month = aug,
publisher = {ACM},
abstract = {Dataflow execution models are used to build highly scalable parallel systems. A programming model that targets parallel dataflow execution must answer the following question: How can parallelism between two dependent nodes in a dataflow graph be exploited? This is difficult when the dataflow language or programming model is implemented by a monad, as is common in the functional community, since expressing dependence between nodes by a monadic bind suggests sequential execution.
Even in monadic constructs that explicitly separate state from computation, problems arise due to the need to reason about opaquely defined state. Specifically, when abstractions of the chosen programming model do not enable adequate reasoning about state, it is difficult to detect parallelism between composed stateful computations.
In this paper, we propose a programming model that enables the composition of stateful computations and still exposes opportunities for parallelization. We also introduce smap, a higher-order function that can exploit parallelism in stateful computations. We present an implementation of our programming model and smap in Haskell and show that basic concepts from functional reactive programming can be built on top of our programming model with little effort. We compare these implementations to a state-of-the-art approach using monad-par and LVars to expose parallelism explicitly and reach the same level of performance, showing that our programming model successfully extracts parallelism that is present in an algorithm. Further evaluation shows that smap is expressive enough to implement parallel reductions and our programming model resolves short-comings of the stream-based programming model for current state-of-the-art big data processing systems.},
acmid = {3342600},
doi = {10.1145/3331545.3342600},
isbn = {978-1-4503-6813-1},
keywords = {conf},
location = {Berlin, Germany},
numpages = {16},
url = {http://doi.acm.org/10.1145/3331545.3342600}
}Downloads
1908_Ertel_Haskell [PDF]
Related Paths
Permalink
- Joonas Multanen, Asif Ali Khan, Pekka Jääskeläinen, Fazal Hameed, Jeronimo Castrillon, "SHRIMP: Efficient Instruction Delivery with Domain Wall Memory", Proceedings of the International Symposium on Low Power Electronics and Design, ACM, 6pp, New York, NY, USA, Jul 2019. [doi] [Bibtex & Downloads]
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory
×Reference
Joonas Multanen, Asif Ali Khan, Pekka Jääskeläinen, Fazal Hameed, Jeronimo Castrillon, "SHRIMP: Efficient Instruction Delivery with Domain Wall Memory", Proceedings of the International Symposium on Low Power Electronics and Design, ACM, 6pp, New York, NY, USA, Jul 2019. [doi]
Bibtex
@InProceedings{multanen_islped19,
author = {Joonas Multanen and Asif Ali Khan and Pekka J{\"a}{\"a}skel{\"a}inen and Fazal Hameed and Jeronimo Castrillon},
title = {{SHRIMP}: Efficient Instruction Delivery with Domain Wall Memory},
booktitle = {Proceedings of the International Symposium on Low Power Electronics and Design},
year = {2019},
month = jul,
series = {ISLPED '19},
location = {Lausanne, Switzerland},
pages = {6pp},
numpages = {6},
publisher = {ACM},
address = {New York, NY, USA},
doi={10.1109/ISLPED.2019.8824954},
url = {https://ieeexplore.ieee.org/document/8824954},
}Downloads
1907_Multanen_ISLPED [PDF]
Related Paths
Permalink
- Andrés Goens, Christian Menard, Jeronimo Castrillon, "On Compact Mappings for Multicore Systems", Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS) (D. Pnevmatikatos and M. Pelcat and M. Jung), Springer, Cham, vol. 11733, pp. 325–335, Jul 2019. [doi] [Bibtex & Downloads]
On Compact Mappings for Multicore Systems
×Reference
Andrés Goens, Christian Menard, Jeronimo Castrillon, "On Compact Mappings for Multicore Systems", Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS) (D. Pnevmatikatos and M. Pelcat and M. Jung), Springer, Cham, vol. 11733, pp. 325–335, Jul 2019. [doi]
Bibtex
@InProceedings{goens_samos19,
author = {Andr{\'e}s Goens and Christian Menard and Jeronimo Castrillon},
title = {On Compact Mappings for Multicore Systems},
booktitle = {Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
year = {2019},
editor = {D. Pnevmatikatos and M. Pelcat and M. Jung},
volume = {11733},
pages = {325--335},
month = jul,
organization = {IEEE},
publisher = {Springer, Cham},
doi = {10.1007/978-3-030-27562-4_23},
isbn = {978-3-030-27561-7},
location = {Pythagorion, Greece},
numpages = {11},
url = {https://link.springer.com/chapter/10.1007/978-3-030-27562-4_23}
}Downloads
1907_Goens_SAMOS [PDF]
Related Paths
Permalink
- Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack Memory Scratch-Pads", Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), ACM, pp. 5–18, New York, NY, USA, Jun 2019. [doi] [Bibtex & Downloads]
Optimizing Tensor Contractions for Embedded Devices with Racetrack Memory Scratch-Pads
×Reference
Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack Memory Scratch-Pads", Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), ACM, pp. 5–18, New York, NY, USA, Jun 2019. [doi]
Abstract
Tensor contraction is a fundamental operation in many algorithms with a plethora of applications ranging from quantum chemistry over fluid dynamics and image processing to machine learning. The performance of tensor computations critically depends on the efficient utilization of on-chip memories. In the context of low-power embedded devices, efficient management of the memory space becomes even more crucial, in order to meet energy constraints. This work aims at investigating strategies for performance- and energy-efficient tensor contractions on embedded systems, using racetrack memory (RTM)-based scratch-pad memory (SPM). Compiler optimizations such as the loop access order and data layout transformations paired with architectural optimizations such as prefetching and preshifting are employed to reduce the shifting overhead in RTMs. Experimental results demonstrate that the proposed optimizations improve the SPM performance and energy consumption by 24% and 74% respectively compared to an iso-capacity SRAM.
Bibtex
@InProceedings{kahn_lctes19,
author = {Asif Ali Khan and Norman A. Rink and Fazal Hameed and Jeronimo Castrillon},
title = {Optimizing Tensor Contractions for Embedded Devices with Racetrack Memory Scratch-Pads},
booktitle = {Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)},
series = {LCTES 2019},
pages = {5--18},
numpages = {12},
numpages = {14},
isbn = {978-1-4503-6724-0/19/06},
doi = {10.1145/3316482.3326351},
url = {http://doi.acm.org/10.1145/3316482.3326351},
acmid = {3326351},
year = {2019},
month = jun,
location = {Phoenix, AZ, USA},
publisher = {ACM},
address = {New York, NY, USA},
abstract = {Tensor contraction is a fundamental operation in many algorithms with a plethora of applications ranging from quantum chemistry over fluid dynamics and image processing to machine learning. The performance of tensor computations critically depends on the efficient utilization of on-chip memories. In the context of low-power embedded devices, efficient management of the memory space becomes even more crucial, in order to meet energy constraints. This work aims at investigating strategies for performance- and energy-efficient tensor contractions on embedded systems, using racetrack memory (RTM)-based scratch-pad memory (SPM). Compiler optimizations such as the loop access order and data layout transformations paired with architectural optimizations such as prefetching and preshifting are employed to reduce the shifting overhead in RTMs. Experimental results demonstrate that the proposed optimizations improve the SPM performance and energy consumption by 24% and 74% respectively compared to an iso-capacity SRAM.},
acmid = {3326351},
}Downloads
1906_Khan_LCTES [PDF]
Related Paths
Permalink
- Norman A. Rink, Jeronimo Castrillon, "TeIL: a type-safe imperative Tensor Intermediate Language", Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming (ARRAY), ACM, pp. 57–68, New York, NY, USA, Jun 2019. [doi] [Bibtex & Downloads]
TeIL: a type-safe imperative Tensor Intermediate Language
×Reference
Norman A. Rink, Jeronimo Castrillon, "TeIL: a type-safe imperative Tensor Intermediate Language", Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming (ARRAY), ACM, pp. 57–68, New York, NY, USA, Jun 2019. [doi]
Abstract
Each of the popular tensor frameworks from the machine learning domain comes with its own language for expressing tensor kernels. Since these tensor languages lack precise specifications, it is impossible to understand and reason about tensor kernels that exhibit unexpected behaviour. In this paper, we give examples of such kernels.
The tensor languages are superficially similar to the well-known functional array languages, for which formal definitions often exist. However, the tensor languages are inherently imperative. In this paper we present TeIL, an imperative tensor intermediate language with precise formal semantics. For the popular tensor languages, TeIL can serve as a common ground on the basis of which precise reasoning about kernels becomes possible. Based on TeIL's formal semantics we develop a type-safety result in the Coq proof assistant.Bibtex
@InProceedings{rink_array19,
author = {Norman A. Rink and Jeronimo Castrillon},
title = {{TeIL}: a type-safe imperative {Tensor Intermediate Language}},
booktitle = {Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming (ARRAY)},
year = {2019},
series = {ARRAY 2019},
pages = {57--68},
address = {New York, NY, USA},
month = jun,
publisher = {ACM},
doi = {10.1145/3315454.3329959},
url = {http://doi.acm.org/10.1145/3315454.3329959},
acmid = {3329959},
isbn = {978-1-4503-6717-2/19/06},
location = {Phoenix, AZ, USA},
numpages = {12},
abstract = {Each of the popular tensor frameworks from the machine learning domain comes with its own language for expressing tensor kernels. Since these tensor languages lack precise specifications, it is impossible to understand and reason about tensor kernels that exhibit unexpected behaviour. In this paper, we give examples of such kernels.
The tensor languages are superficially similar to the well-known functional array languages, for which formal definitions often exist. However, the tensor languages are inherently imperative. In this paper we present TeIL, an imperative tensor intermediate language with precise formal semantics. For the popular tensor languages, TeIL can serve as a common ground on the basis of which precise reasoning about kernels becomes possible. Based on TeIL's formal semantics we develop a type-safety result in the Coq proof assistant.},
}Downloads
1906_Rink_Array [PDF]
Related Paths
Permalink
- Marten Lohstroh, Martin Schoeberl, Andrés Goens, Armin Wasicek, Christopher Gill, Marjan Sirjani, Edward A Lee, "Actors Revisited for Time-Critical Systems", Proceedings of the 56th annual Design Automation Conference, ACM, 4pp, Las Vegas, NV, USA, Jun 2019. [doi] [Bibtex & Downloads]
Actors Revisited for Time-Critical Systems
×Reference
Marten Lohstroh, Martin Schoeberl, Andrés Goens, Armin Wasicek, Christopher Gill, Marjan Sirjani, Edward A Lee, "Actors Revisited for Time-Critical Systems", Proceedings of the 56th annual Design Automation Conference, ACM, 4pp, Las Vegas, NV, USA, Jun 2019. [doi]
Bibtex
@InProceedings{lohstroh_dac19,
title={Actors Revisited for Time-Critical Systems},
author={Lohstroh, Marten and Schoeberl, Martin and Goens, Andr{\'e}s and Wasicek, Armin and Gill, Christopher and Sirjani, Marjan and Lee, Edward A},
year={2019},
booktitle = {Proceedings of the 56th annual Design Automation Conference},
year = {2019},
series = {DAC 2019},
pages = {4pp},
address = {Las Vegas, NV, USA},
month = jun,
publisher = {ACM},
keywords = {conf},
location = {Las Vegas, NV, USA},
numpages = {4},
url = {http://doi.acm.org/10.1145/3316781.3323469},
doi = {10.1145/3316781.3323469},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Ertel, Justus Adam, Norman A. Rink, Andrés Goens, Jeronimo Castrillon, "Category-Theoretic Foundations of ``STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism''", In CoRR, vol. abs/1906.12098, Jun 2019. [Bibtex & Downloads]
Category-Theoretic Foundations of ``STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism''
×Reference
Sebastian Ertel, Justus Adam, Norman A. Rink, Andrés Goens, Jeronimo Castrillon, "Category-Theoretic Foundations of ``STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism''", In CoRR, vol. abs/1906.12098, Jun 2019.
Bibtex
@Article{ertel_haskellsup19,
author = {Sebastian Ertel and Justus Adam and Norman A. Rink and Andr{\'{e}}s Goens and Jeronimo Castrillon},
title = {Category-Theoretic Foundations of ``STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism''},
journal = {CoRR},
year = {2019},
volume = {abs/1906.12098},
month = jun,
archiveprefix = {arXiv},
biburl = {https://dblp.org/rec/bib/journals/corr/abs-1906-12098},
eprint = {1906.12098},
url = {http://arxiv.org/abs/1906.12098}
}Downloads
1906_Ertel_Haskellsupp [PDF]
Related Paths
Permalink
- Hasna Bouraoui, Jeronimo Castrillon, Chadlia Jerad, "Comparing Dataflow and OpenMP Programming for Speaker Recognition Applications", Proceedings of the 10th Workshop and 8th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'19), co-located with 14th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 4:1–4:6, New York, NY, USA, Jan 2019. [doi] [Bibtex & Downloads]
Comparing Dataflow and OpenMP Programming for Speaker Recognition Applications
×Reference
Hasna Bouraoui, Jeronimo Castrillon, Chadlia Jerad, "Comparing Dataflow and OpenMP Programming for Speaker Recognition Applications", Proceedings of the 10th Workshop and 8th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'19), co-located with 14th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 4:1–4:6, New York, NY, USA, Jan 2019. [doi]
Bibtex
@InProceedings{bouraoui_parma19,
author = {Hasna Bouraoui and Jeronimo Castrillon and Chadlia Jerad},
title = {Comparing Dataflow and OpenMP Programming for Speaker Recognition Applications},
booktitle = {Proceedings of the 10th Workshop and 8th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'19), co-located with 14th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)},
year = {2019},
series = {PARMA-DITAM 2019},
pages = {4:1--4:6},
articleno = {4},
numpages = {6},
address = {New York, NY, USA},
month = jan,
publisher = {ACM},
isbn = {978-1-4503-6321-1},
url = {http://doi.acm.org/10.1145/3310411.3310417},
doi = {10.1145/3310411.3310417},
acmid = {3310417},
location = {Valencia, Spain},
numpages = {6}
}Downloads
1901_Bouraoui_PARMA [PDF]
Related Paths
Permalink
- Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart Parkin, Jeronimo Castrillon, "RTSim: A Cycle-accurate Simulator for Racetrack Memories", In IEEE Computer Architecture Letters, IEEE, vol. 18, no. 1, pp. 43–46, Jan 2019. [doi] [Bibtex & Downloads]
RTSim: A Cycle-accurate Simulator for Racetrack Memories
×Reference
Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart Parkin, Jeronimo Castrillon, "RTSim: A Cycle-accurate Simulator for Racetrack Memories", In IEEE Computer Architecture Letters, IEEE, vol. 18, no. 1, pp. 43–46, Jan 2019. [doi]
Bibtex
@Article{khan_ieeecal19,
author = {Asif Ali Khan and Fazal Hameed and Robin Bl{\"a}sing and Stuart Parkin and Jeronimo Castrillon},
title = {{RTS}im: A Cycle-accurate Simulator for Racetrack Memories},
journal = {IEEE Computer Architecture Letters},
year = {2019},
volume = {18},
number = {1},
pages = {43--46},
month = jan,
doi = {10.1109/LCA.2019.2899306},
issn = {1556-6056},
publisher = {IEEE},
url = {https://ieeexplore.ieee.org/document/8642352}
}Downloads
1902_khan_IEEECAL [PDF]
Related Paths
Permalink
2018
- Adilla Susungi, Norman A. Rink, Albert Cohen, Jeronimo Castrillon, Claude Tadonki, "Meta-programming for Cross-Domain Tensor Optimizations", Proceedings of 17th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE'18), ACM, pp. 79–92, New York, NY, USA, Nov 2018. [doi] [Bibtex & Downloads]
Meta-programming for Cross-Domain Tensor Optimizations
×Reference
Adilla Susungi, Norman A. Rink, Albert Cohen, Jeronimo Castrillon, Claude Tadonki, "Meta-programming for Cross-Domain Tensor Optimizations", Proceedings of 17th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE'18), ACM, pp. 79–92, New York, NY, USA, Nov 2018. [doi]
Bibtex
@InProceedings{rink_gpce18,
author = {Adilla Susungi and Norman A. Rink and Albert Cohen and Jeronimo Castrillon and Claude Tadonki},
title = {Meta-programming for Cross-Domain Tensor Optimizations},
booktitle = {Proceedings of 17th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE'18)},
year = {2018},
series = {GPCE 2018},
pages = {79--92},
numpages = {14},
address = {New York, NY, USA},
month = nov,
publisher = {ACM},
keywords = {conf},
location = {Boston, MA, USA},
isbn = {978-1-4503-6045-6},
url = {http://doi.acm.org/10.1145/3278122.3278131},
doi = {10.1145/3278122.3278131},
acmid = {3278131},
}Downloads
1811_Rink_GPCE [PDF]
Related Paths
Permalink
- Andrés Goens, Christian Menard, Jeronimo Castrillon, "On the Representation of Mappings to Multicores", Proceedings of the IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-18), pp. 184–191, Vietnam National University, Hanoi, Vietnam, Sep 2018. [doi] [Bibtex & Downloads]
On the Representation of Mappings to Multicores
×Reference
Andrés Goens, Christian Menard, Jeronimo Castrillon, "On the Representation of Mappings to Multicores", Proceedings of the IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-18), pp. 184–191, Vietnam National University, Hanoi, Vietnam, Sep 2018. [doi]
Abstract
Application requirements for embedded systems are growing rapidly, as is the complexity of systems designed to execute them. A common abstraction used to tame this growing complexity is that of a mapping, which assigns parts of an application to different hardware resources. Modern flows need to explore an intractably large design space of mappings, and be able to quickly find near-optimal mappings for different objectives, sometimes at runtime. With systems featuring thousands of cores in the near horizon, we need methods to make this exploration step truly scalable. In this paper we argue that the mathematical representation of a mapping is central to achieve this. We present different representations and how these could be applied to different contexts and objectives, like complex design- space exploration meta-heuristics or efficient runtime systems.
Bibtex
@InProceedings{goen_mcsoc18,
author = {Andr\'{e}s Goens and Christian Menard and Jeronimo Castrillon},
title = {On the Representation of Mappings to Multicores},
booktitle = {Proceedings of the IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-18)},
year = {2018},
address = {Vietnam National University, Hanoi, Vietnam},
month = sep,
pages = {184--191},
doi = {10.1109/MCSoC2018.2018.00039},
url = {https://ieeexplore.ieee.org/document/8540232},
isbn = {978-1-5386-6689-0/18/},
abstract = {Application requirements for embedded systems are growing rapidly, as is the complexity of systems designed to execute them. A common abstraction used to tame this growing complexity is that of a mapping, which assigns parts of an application to different hardware resources. Modern flows need to explore an intractably large design space of mappings, and be able to quickly find near-optimal mappings for different objectives, sometimes at runtime. With systems featuring thousands of cores in the near horizon, we need methods to make this exploration step truly scalable. In this paper we argue that the mathematical representation of a mapping is central to achieve this. We present different representations and how these could be applied to different contexts and objectives, like complex design- space exploration meta-heuristics or efficient runtime systems.},
}Downloads
1809_Goens_MCSoC [PDF]
Related Paths
Permalink
- Til Jasper Ullrich, "Detection and exploitation of data-parallelism in assignments of multi-dimensional tensors", Bachelor's thesis, TU Dresden, Dresden, Germany, 8/2018. [Bibtex & Downloads]
Detection and exploitation of data-parallelism in assignments of multi-dimensional tensors
×Reference
Til Jasper Ullrich, "Detection and exploitation of data-parallelism in assignments of multi-dimensional tensors", Bachelor's thesis, TU Dresden, Dresden, Germany, 8/2018.
Bibtex
@bachelorsthesis{TilJasper2018Detect,
title={Detection and exploitation of data-parallelism in assignments of multi-dimensional tensors},
author={Til Jasper Ullrich},
year={2018},
month={8},
note={Qucosa: http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa2-319722},
address={Dresden, Germany},
school={TU Dresden},
}Downloads
1808_Ullrich [PDF]
Related Paths
Permalink
- Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi] [Bibtex & Downloads]
A Hardware/Software Stack for Heterogeneous Systems
×Reference
Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi]
Abstract
Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.
Bibtex
@Article{castrillon_tmscs17,
author = {Jeronimo Castrillon and Matthias Lieber and Sascha Kl{\"u}ppelholz and Marcus V{\"o}lp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andr\'{e}s Goens and Sebastian Haas and Dirk Habich and Hermann H{\"a}rtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen M{\"a}rcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt and Sascha Wunderlich},
title = {A Hardware/Software Stack for Heterogeneous Systems},
journal = {IEEE Transactions on Multi-Scale Computing Systems},
year = {2018},
month = jul,
volume={4},
number={3},
pages={243-259},
abstract = {Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.},
doi = {10.1109/TMSCS.2017.2771750},
issn = {2332-7766},
url = {http://ieeexplore.ieee.org/document/8103042/}
}Downloads
1711_Castrillon_TMSCS [PDF]
Related Paths
Permalink
- Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Performance and Energy Efficient Design of STT-RAM Last-Level-Cache", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, no. 6, pp. 1059–1072, Jun 2018. [doi] [Bibtex & Downloads]
Performance and Energy Efficient Design of STT-RAM Last-Level-Cache
×Reference
Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Performance and Energy Efficient Design of STT-RAM Last-Level-Cache", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, no. 6, pp. 1059–1072, Jun 2018. [doi]
Abstract
Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM caches. However, recently proposed STT-RAM cache architectures unnecessarily dissipate energy by fetching unneeded cache lines (CLs) into the row buffer (RB). In this paper, we propose a selective read policy for the STT-RAM which fetches those CLs into the RB that are likely to be reused. In addition, we propose a tags-update policy that reduces the number of STT-RAM writebacks. This reduces the number of reads/writes and thereby decreases the energy consumption. To reduce the latency penalty of our selective read policy, we propose the following performance optimizations: 1) an RB tags-bypass policy that reduces STT-RAM access latency; 2) an LLC data cache that stores the CLs that are likely to be used in the near future; 3) an address organization scheme that simultaneously reduces LLC access latency and miss rate; and 4) a tags-to-column mapping policy that improves access parallelism. For evaluation, we implement our proposed architecture in the Zesto simulator and run different combinations of SPEC2006 benchmarks on an eight-core system. We compare our approach with a recently proposed STT-RAM LLC with subarray parallelism support and show that our synergistic policies reduce the average LLC dynamic energy consumption by 75% and improve the system performance by 6.5%. Compared with the state-of-the-art DRAM LLC with subarray parallelism, our architecture reduces the LLC dynamic energy consumption by 82% and improves system performance by 6.8%.
Bibtex
@Article{hameed_tvlsi18,
author = {Fazal Hameed and Asif Ali Khan and Jeronimo Castrillon},
title = {Performance and Energy Efficient Design of STT-RAM Last-Level-Cache},
journal = {IEEE Transactions on Very Large Scale Integration Systems (TVLSI)},
year = {2018},
volume = {26},
number = {6},
pages = {1059--1072},
month = jun,
abstract = {Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM caches. However, recently proposed STT-RAM cache architectures unnecessarily dissipate energy by fetching unneeded cache lines (CLs) into the row buffer (RB). In this paper, we propose a selective read policy for the STT-RAM which fetches those CLs into the RB that are likely to be reused. In addition, we propose a tags-update policy that reduces the number of STT-RAM writebacks. This reduces the number of reads/writes and thereby decreases the energy consumption. To reduce the latency penalty of our selective read policy, we propose the following performance optimizations: 1) an RB tags-bypass policy that reduces STT-RAM access latency; 2) an LLC data cache that stores the CLs that are likely to be used in the near future; 3) an address organization scheme that simultaneously reduces LLC access latency and miss rate; and 4) a tags-to-column mapping policy that improves access parallelism. For evaluation, we implement our proposed architecture in the Zesto simulator and run different combinations of SPEC2006 benchmarks on an eight-core system. We compare our approach with a recently proposed STT-RAM LLC with subarray parallelism support and show that our synergistic policies reduce the average LLC dynamic energy consumption by 75\% and improve the system performance by 6.5\%. Compared with the state-of-the-art DRAM LLC with subarray parallelism, our architecture reduces the LLC dynamic energy consumption by 82\% and improves system performance by 6.8\%.},
doi = {10.1109/TVLSI.2018.2804938},
file = {:/Users/jeronimocastrillon/Documents/Academic/mypapers/1803_Hameed_TVLSI.pdf:PDF},
issn = {1063-8210},
numpages = {14},
url = {http://ieeexplore.ieee.org/document/8307465/}
}Downloads
1803_Hameed_TVLSI [PDF]
Related Paths
Permalink
- Sven Karol, Tobias Nett, Jeronimo Castrillon, Ivo F. Sbalzarini, "A Domain-Specific Language and Editor for Parallel Particle Methods", In ACM Transactions on Mathematical Software (TOMS), ACM, vol. 44, no. 3, pp. 32, New York, NY, USA, Mar 2018. [doi] [Bibtex & Downloads]
A Domain-Specific Language and Editor for Parallel Particle Methods
×Reference
Sven Karol, Tobias Nett, Jeronimo Castrillon, Ivo F. Sbalzarini, "A Domain-Specific Language and Editor for Parallel Particle Methods", In ACM Transactions on Mathematical Software (TOMS), ACM, vol. 44, no. 3, pp. 32, New York, NY, USA, Mar 2018. [doi]
Abstract
Domain-specific languages (DSLs) are of increasing importance in scientific high-performance computing to reduce development costs, raise the level of abstraction and, thus, ease scientific programming. However, designing DSLs is not easy, as it requires knowledge of the application domain and experience in language engineering and compilers. Consequently, many DSLs follow a weak approach using macros or text generators, which lack many of the features that make a DSL comfortable for programmers. Some of these features –e.g., syntax highlighting, type inference, error reporting– are easily provided by language workbenches, which combine language engineering techniques and tools in a common ecosystem. In this paper, we present the Parallel Particle-Mesh Environment (PPME), a DSL and development environment for numerical simulations based on particle methods and hybrid particle-mesh methods. PPME uses the Meta Programming System (MPS), a projectional language workbench. PPME is the successor of the Parallel Particle-Mesh Language, a Fortran-based DSL that uses conventional implementation strategies. We analyze and compare both languages and demonstrate how the programmer’s experience is improved using static analyses and projectional editing, i.e., code-structure editing, constrained by syntax, as opposed to free-text editing. We present an explicit domain model for particle abstractions and the first formal type system for partircle methods.
Bibtex
@Article{karol_toms18,
author = {Karol, Sven and Nett, Tobias and Castrillon, Jeronimo and Sbalzarini, Ivo F.},
title = {A Domain-Specific Language and Editor for Parallel Particle Methods},
journal = {ACM Transactions on Mathematical Software (TOMS)},
issue_date = {March 2018},
volume = {44},
number = {3},
month = mar,
year = {2018},
issn = {0098-3500},
pages = {34:1--34:32},
articleno = {34},
numpages = {32},
url = {http://doi.acm.org/10.1145/3175659},
doi = {10.1145/3175659},
acmid = {3175659},
publisher = {ACM},
address = {New York, NY, USA},
pages = {32},
abstract = {
Domain-specific languages (DSLs) are of increasing importance in scientific high-performance computing to reduce development costs, raise the level of abstraction and, thus, ease scientific programming. However, designing DSLs is not easy, as it requires knowledge of the application domain and experience in language engineering and compilers. Consequently, many DSLs follow a weak approach using macros or text generators, which lack many of the features that make a DSL comfortable for programmers. Some of these features --e.g., syntax highlighting, type inference, error reporting-- are easily provided by language workbenches, which combine language engineering techniques and tools in a common ecosystem. In this paper, we present the Parallel Particle-Mesh Environment (PPME), a DSL and development environment for numerical simulations based on particle methods and hybrid particle-mesh methods. PPME uses the Meta Programming System (MPS), a projectional language workbench. PPME is the successor of the Parallel Particle-Mesh Language, a Fortran-based DSL that uses conventional implementation strategies. We analyze and compare both languages and demonstrate how the programmer’s experience is improved using static analyses and projectional editing, i.e., code-structure editing, constrained by syntax, as opposed to free-text editing. We present an explicit domain model for particle abstractions and the first formal type system for partircle methods.},
}Downloads
1709_Karol_TOMS-arxiv [PDF]
Related Paths
Biological Systems Path, Orchestration Path
Permalink
- Fazal Hameed, Jeronimo Castrillon, "STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement", Proceedings of the 9th Annual Non-Volatile Memories Workshop (NVMW 2018), Mar 2018. [Bibtex & Downloads]
STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement
×Reference
Fazal Hameed, Jeronimo Castrillon, "STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement", Proceedings of the 9th Annual Non-Volatile Memories Workshop (NVMW 2018), Mar 2018.
Bibtex
@InProceedings{hameed_nvmw18,
author = {Fazal Hameed and Jeronimo Castrillon},
title = {STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement},
booktitle = {Proceedings of the 9th Annual Non-Volatile Memories Workshop (NVMW 2018)},
year = {2018},
month = mar,
location = {San Diego, CA, USA},
numpages = {2}
}Downloads
1803_Hameed_NVMW [PDF]
Related Paths
Permalink
- Sebastian Ertel, Andrés Goens, Justus Adam, Jeronimo Castrillon, "Compiling for Concise Code and Efficient I/O", Proceedings of the 27th International Conference on Compiler Construction (CC 2018), ACM, pp. 104–115, New York, NY, USA, Feb 2018. [doi] [Bibtex & Downloads]
Compiling for Concise Code and Efficient I/O
×Reference
Sebastian Ertel, Andrés Goens, Justus Adam, Jeronimo Castrillon, "Compiling for Concise Code and Efficient I/O", Proceedings of the 27th International Conference on Compiler Construction (CC 2018), ACM, pp. 104–115, New York, NY, USA, Feb 2018. [doi]
Abstract
Large infrastructures of Internet companies, such as Facebook and Twitter, are composed of several layers of micro-services. While this modularity provides scalability to the system, the I/O associated with each service request strongly impacts its performance. In this context, writing concise programs which execute I/O efficiently is especially challenging. In this paper, we introduce Ÿauhau, a novel compile-time solution. Ÿauhau reduces the number of I/O calls through rewrites on a simple expression language. To execute I/O concurrently, it lowers the expression language to a dataflow representation. Our approach can be used alongside an existing programming language, permitting the use of legacy code. We describe an implementation in the JVM and use it to evaluate our approach. Experiments show that Ÿauhau can significantly improve I/O, both in terms of the number of I/O calls and concurrent execution. Ÿauhau outperforms state-of-the-art approaches with similar goals.
Bibtex
@InProceedings{ertel_cc18,
author = {Sebastian Ertel and Andr\'{e}s Goens and Justus Adam and Jeronimo Castrillon},
title = {Compiling for Concise Code and Efficient I/O},
booktitle = {Proceedings of the 27th International Conference on Compiler Construction (CC 2018)},
series = {CC 2018},
year = {2018},
month = feb,
location = {Vienna, Austria},
publisher = {ACM},
numpages = {12},
pages = {104--115},
doi = {10.1145/3178372.3179505},
url = {https://dl.acm.org/citation.cfm?id=3179505},
acmid = {3179505},
address = {New York, NY, USA},
abstract = {Large infrastructures of Internet companies, such as Facebook and Twitter, are composed of several layers of micro-services. While this modularity provides scalability to the system, the I/O associated with each service request strongly impacts its performance. In this context, writing concise programs which execute I/O efficiently is especially challenging. In this paper, we introduce Ÿauhau, a novel compile-time solution. Ÿauhau reduces the number of I/O calls through rewrites on a simple expression language. To execute I/O concurrently, it lowers the expression language to a dataflow representation. Our approach can be used alongside an existing programming language, permitting the use of legacy code. We describe an implementation in the JVM and use it to evaluate our approach. Experiments show that Ÿauhau can significantly improve I/O, both in terms of the number of I/O calls and concurrent execution. Ÿauhau outperforms state-of-the-art approaches with similar goals.},
}Downloads
cc-2018-slides [PDF]
1802_Ertel_CC [PDF]
Related Paths
Permalink
- Sebastian Ertel, Justus Adam, Jeronimo Castrillon, "Supporting Fine-grained Dataflow Parallelism in Big Data Systems", Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM), ACM, pp. 41–50, New York, NY, USA, Feb 2018. [doi] [Bibtex & Downloads]
Supporting Fine-grained Dataflow Parallelism in Big Data Systems
×Reference
Sebastian Ertel, Justus Adam, Jeronimo Castrillon, "Supporting Fine-grained Dataflow Parallelism in Big Data Systems", Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM), ACM, pp. 41–50, New York, NY, USA, Feb 2018. [doi]
Abstract
Big data systems scale with the number of cores in a cluster for the parts of an application that can be executed in data parallel fashion. It has been recently reported, however, that these systems fail to translate hardware improvements, such as increased network bandwidth, into a higher throughput. This is particularly the case for applications that have inherent sequential, computationally intensive phases. In this paper, we analyze the data processing cores of state-of-the-art big data systems to find the cause for these scalability problems. We identify design patterns in the code that are suitable for pipeline and task-level parallelism, potentially increasing application performance. As a proof of concept, we rewrite parts of the Hadoop MapReduce framework in an implicit parallel language that exploits this parallelism without adding code complexity. Our experiments on a data analytics workload show throughput speedups of up to 3.5x.
Bibtex
@InProceedings{ertel_pmam18,
author = {Sebastian Ertel and Justus Adam and Jeronimo Castrillon},
title = {Supporting Fine-grained Dataflow Parallelism in Big Data Systems},
booktitle = {Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM)},
year = {2018},
series = {PMAM'18},
address = {New York, NY, USA},
month = feb,
publisher = {ACM},
doi = {10.1145/3178442.3178447},
isbn = {978-1-4503-5645-9},
location = {Vienna, Austria},
pages = {41--50},
numpages = {10},
acmid = {3178447},
url = {http://doi.acm.org/10.1145/3178442.3178447},
abstract = {Big data systems scale with the number of cores in a cluster for the parts of an application that can be executed in data parallel fashion. It has been recently reported, however, that these systems fail to translate hardware improvements, such as increased network bandwidth, into a higher throughput. This is particularly the case for applications that have inherent sequential, computationally intensive phases. In this paper, we analyze the data processing cores of state-of-the-art big data systems to find the cause for these scalability problems. We identify design patterns in the code that are suitable for pipeline and task-level parallelism, potentially increasing application performance. As a proof of concept, we rewrite parts of the Hadoop MapReduce framework in an implicit parallel language that exploits this parallelism without adding code complexity. Our experiments on a data analytics workload show throughput speedups of up to 3.5x.},
}Downloads
pmam-2018-slides [PDF]
1802_Ertel_PMAM [PDF]
Related Paths
Permalink
- Norman A. Rink, Immo Huismann, Adilla Susungi, Jeronimo Castrillon, Jörg Stiller, Jochen Fröhlich, Claude Tadonki, "CFDlang: High-level Code Generation for High-order Methods in Fluid Dynamics", Proceedings of the 3rd International Workshop on Real World Domain Specific Languages (RWDSL 2018), ACM, pp. 5:1–5:10, New York, NY, USA, Feb 2018. [doi] [Bibtex & Downloads]
CFDlang: High-level Code Generation for High-order Methods in Fluid Dynamics
×Reference
Norman A. Rink, Immo Huismann, Adilla Susungi, Jeronimo Castrillon, Jörg Stiller, Jochen Fröhlich, Claude Tadonki, "CFDlang: High-level Code Generation for High-order Methods in Fluid Dynamics", Proceedings of the 3rd International Workshop on Real World Domain Specific Languages (RWDSL 2018), ACM, pp. 5:1–5:10, New York, NY, USA, Feb 2018. [doi]
Abstract
Numerical simulations continue to enable fast and enormous progress in science and engineering. Writing efficient numerical codes is a difficult challenge that encompasses a variety of tasks from designing the right algorithms to exploiting the full potential of a platform's architecture. Domain-specific languages (DSLs) can ease these tasks by offering the right abstractions for expressing numerical problems. With the aid of domain knowledge, efficient code can then be generated automatically from abstract expressions. In this work, we present the CFDlang DSL for expressing tensor operations that constitute the performance-critical code sections in a class of real numerical applications from fluid dynamics. We demonstrate that CFDlang can be used to generate code automatically that performs as well, if not better, than carefully hand-optimized code.
Bibtex
@InProceedings{rink_rwdsl18,
author = {Norman A. Rink and Immo Huismann and Adilla Susungi and Jeronimo Castrillon and J{\"o}rg Stiller and Jochen Fr{\"o}hlich and Claude Tadonki},
title = {CFDlang: High-level Code Generation for High-order Methods in Fluid Dynamics},
booktitle = {Proceedings of the 3rd International Workshop on Real World Domain Specific Languages (RWDSL 2018)},
year = {2018},
series = {RWDSL2018},
pages = {5:1--5:10},
address = {New York, NY, USA},
month = feb,
publisher = {ACM},
abstract = {Numerical simulations continue to enable fast and enormous progress in science and engineering. Writing efficient numerical codes is a difficult challenge that encompasses a variety of tasks from designing the right algorithms to exploiting the full potential of a platform's architecture. Domain-specific languages (DSLs) can ease these tasks by offering the right abstractions for expressing numerical problems. With the aid of domain knowledge, efficient code can then be generated automatically from abstract expressions. In this work, we present the CFDlang DSL for expressing tensor operations that constitute the performance-critical code sections in a class of real numerical applications from fluid dynamics. We demonstrate that CFDlang can be used to generate code automatically that performs as well, if not better, than carefully hand-optimized code.},
acmid = {3183900},
articleno = {5},
doi = {10.1145/3183895.3183900},
isbn = {978-1-4503-6355-6},
location = {Vienna, Austria},
numpages = {10},
url = {http://doi.acm.org/10.1145/3183895.3183900}
}Downloads
1802_Rink_RWDSL [PDF]
Related Paths
Permalink
- Hermann Härtig, Nils Asmussen, Jeronimo Castrillon, Adam Lackorzynski, Michael Roitzsch, Carsten Weinhold, Akash Kumar, "Extremely Heterogeneous Systems – Not Just For Niches", In Proceeding: Extreme Heterogeneity Workshop, Feb 2018. [Bibtex & Downloads]
Extremely Heterogeneous Systems – Not Just For Niches
×Reference
Hermann Härtig, Nils Asmussen, Jeronimo Castrillon, Adam Lackorzynski, Michael Roitzsch, Carsten Weinhold, Akash Kumar, "Extremely Heterogeneous Systems – Not Just For Niches", In Proceeding: Extreme Heterogeneity Workshop, Feb 2018.
Bibtex
@InProceedings{haertig_ehw18,
author = {Hermann H{\"a}rtig and Nils Asmussen and Jeronimo Castrillon and Adam Lackorzynski and Michael Roitzsch and Carsten Weinhold and Akash Kumar},
title = {Extremely Heterogeneous Systems -- Not Just For Niches},
booktitle = {Extreme Heterogeneity Workshop},
year = {2018},
month = feb,
note = {(Workshop took place over remote conferencing)},
location = {Gaithersburg, MD, USA}
}Downloads
1802_Haertig_EHW [PDF]
Related Paths
Permalink
- Robert Khasanov, Andrés Goens, Jeronimo Castrillon, "Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap", Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'18), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 20–25, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]
Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap
×Reference
Robert Khasanov, Andrés Goens, Jeronimo Castrillon, "Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap", Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'18), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 20–25, New York, NY, USA, Jan 2018. [doi]
Abstract
Modern embedded systems are rapidly increasing their complexity, both in terms of numbers of cores, as well as heterogeneity. To generate efficient code for these systems, it is common to leverage formal models of computation.
Among these, the dataflow model of Kahn Process Networks (KPN) is widespread because it is expressive but guarantees a deterministic execution. However, the KPN model is ill-suited to expose data-level parallelism, since this has to be made explicit in the process network. This is aggravated by the fact that its most common execution model, Kahn-MacQueen, poses restrictive conditions on the scheduling of data-parallel processes, leading to an inefficient execution. In this paper we present a novel extension to the KPN model and a relaxed execution strategy that addresses this problem, while keeping the deterministic KPN semantics. It improves run-time adaptivity in malleable way and provides implicit parallelism. We evaluate our approach on two architectures, improving the performance of a benchmark by up to 25.6% on an Intel chip with hyper-threading, and by up to 78.0% on a heterogeneous embedded ARM big.LITTLE architecture.Bibtex
@InProceedings{khasanov_parma18,
author = {Robert Khasanov and Andr\'{e}s Goens and Jeronimo Castrillon},
title = {Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap},
booktitle = {Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'18), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)},
series = {PARMA-DITAM '18},
isbn = {978-1-4503-6444-7},
pages = {20--25},
year = {2018},
month = jan,
numpages = {6},
url = {http://doi.acm.org/10.1145/3183767.3183790},
doi = {10.1145/3183767.3183790},
acmid = {3183790},
publisher = {ACM},
address = {New York, NY, USA},
location = {Manchester, United Kingdom},
abstract = {Modern embedded systems are rapidly increasing their complexity, both in terms of numbers of cores, as well as heterogeneity. To generate efficient code for these systems, it is common to leverage formal models of computation.
Among these, the dataflow model of Kahn Process Networks (KPN) is widespread because it is expressive but guarantees a deterministic execution. However, the KPN model is ill-suited to expose data-level parallelism, since this has to be made explicit in the process network. This is aggravated by the fact that its most common execution model, Kahn-MacQueen, poses restrictive conditions on the scheduling of data-parallel processes, leading to an inefficient execution. In this paper we present a novel extension to the KPN model and a relaxed execution strategy that addresses this problem, while keeping the deterministic KPN semantics. It improves run-time adaptivity in malleable way and provides implicit parallelism. We evaluate our approach on two architectures, improving the performance of a benchmark by up to 25.6% on an Intel chip with hyper-threading, and by up to 78.0% on a heterogeneous embedded ARM big.LITTLE architecture.},
}Downloads
1801_Khasanov_PARMA-DITAM [PDF]
Related Paths
Permalink
- Andrés Goens, Sebastian Ertel, Justus Adam, Jeronimo Castrillon, "Level Graphs: Generating Benchmarks for Concurrency Optimizations in Compilers", Proceedings of the 11th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG'2018), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Jan 2018. [Bibtex & Downloads]
Level Graphs: Generating Benchmarks for Concurrency Optimizations in Compilers
×Reference
Andrés Goens, Sebastian Ertel, Justus Adam, Jeronimo Castrillon, "Level Graphs: Generating Benchmarks for Concurrency Optimizations in Compilers", Proceedings of the 11th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG'2018), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Jan 2018.
Bibtex
@InProceedings{goens_multiprog18,
author = {Andr{\'e}s Goens and Sebastian Ertel and Justus Adam and Jeronimo Castrillon},
title = {Level Graphs: Generating Benchmarks for Concurrency Optimizations in Compilers},
booktitle = {Proceedings of the 11th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG'2018), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)},
year = {2018},
url = {http://research.ac.upc.edu/multiprog/multiprog2018/papers/MULTIPROG-2018_Goens.pdf},
month = jan,
location = {Manchester, United Kingdom}
}Downloads
1801_Goens_MULTIRPOG [PDF]
Related Paths
Permalink
- Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon, "NVMain Extension for Multi-Level Cache Systems", Proceedings of the 10th RAPIDO Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 7:1–7:6, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]
NVMain Extension for Multi-Level Cache Systems
×Reference
Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon, "NVMain Extension for Multi-Level Cache Systems", Proceedings of the 10th RAPIDO Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 7:1–7:6, New York, NY, USA, Jan 2018. [doi]
Bibtex
@InProceedings{khan_rapido18,
author = {Asif Ali Khan and Fazal Hameed and Jeronimo Castrillon},
title = {NVMain Extension for Multi-Level Cache Systems},
booktitle = {Proceedings of the 10th RAPIDO Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)},
series = {RAPIDO '18},
year = {2018},
month = jan,
pages = {7:1--7:6},
articleno = {7},
numpages = {6},
url = {http://doi.acm.org/10.1145/3180665.3180672},
doi = {10.1145/3180665.3180672},
acmid = {3180672},
publisher = {ACM},
address = {New York, NY, USA},
location = {Manchester, United Kingdom},
isbn = {978-1-4503-6417-1},
}Downloads
1801_Khan_RAPIDO [PDF]
Related Paths
Permalink
- Daniel Gburek, Christel Baier, "Bisimulations, Logics, and Trace Distributions for Stochastic Systems with Rewards", Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (Part of CPS Week), ACM, pp. 31–40, New York, NY, USA, 2018. [doi] [Bibtex & Downloads]
Bisimulations, Logics, and Trace Distributions for Stochastic Systems with Rewards
×Reference
Daniel Gburek, Christel Baier, "Bisimulations, Logics, and Trace Distributions for Stochastic Systems with Rewards", Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (Part of CPS Week), ACM, pp. 31–40, New York, NY, USA, 2018. [doi]
Bibtex
@inproceedings{Gburek:2018:BLT:3178126.3178139,
author = {Gburek, Daniel and Baier, Christel},
title = {Bisimulations, Logics, and Trace Distributions for Stochastic Systems with Rewards},
booktitle = {Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (Part of CPS Week)},
series = {HSCC '18},
year = {2018},
isbn = {978-1-4503-5642-8},
location = {Porto, Portugal},
pages = {31--40},
numpages = {10},
url = {http://doi.acm.org/10.1145/3178126.3178139},
doi = {10.1145/3178126.3178139},
acmid = {3178139},
publisher = {ACM},
address = {New York, NY, USA},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Norman A. Rink, "Modeling of languages for tensor manipulation", In CoRR, vol. abs/1801.08771, 2018. [Bibtex & Downloads]
Modeling of languages for tensor manipulation
×Reference
Norman A. Rink, "Modeling of languages for tensor manipulation", In CoRR, vol. abs/1801.08771, 2018.
Bibtex
@article{Rink18,
author = {Norman A. Rink},
title = {Modeling of languages for tensor manipulation},
journal = {CoRR},
volume = {abs/1801.08771},
year = {2018},
url = {http://arxiv.org/abs/1801.08771},
archivePrefix = {arXiv},
eprint = {1801.08771},
biburl = {https://dblp.org/rec/bib/journals/corr/abs-1801-08771},
bibsource = {dblp computer science bibliography, https://dblp.org}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
2017
- Fazal Hameed, Christian Menard, Jeronimo Castrillon, "Efficient STT-RAM Last-Level-Cache Architecture to replace DRAM Cache", Proceedings of the International Symposium on Memory Systems (MemSys'17), ACM, pp. 141–151, New York, NY, USA, Oct 2017. [doi] [Bibtex & Downloads]
Efficient STT-RAM Last-Level-Cache Architecture to replace DRAM Cache
×Reference
Fazal Hameed, Christian Menard, Jeronimo Castrillon, "Efficient STT-RAM Last-Level-Cache Architecture to replace DRAM Cache", Proceedings of the International Symposium on Memory Systems (MemSys'17), ACM, pp. 141–151, New York, NY, USA, Oct 2017. [doi]
Bibtex
@InProceedings{hameed_memsys17,
author = {Fazal Hameed and Christian Menard and Jeronimo Castrillon},
title = {Efficient STT-RAM Last-Level-Cache Architecture to replace DRAM Cache},
booktitle = {Proceedings of the International Symposium on Memory Systems (MemSys'17)},
series = {MEMSYS '17},
year = {2017},
month = oct,
isbn = {978-1-4503-5335-9},
location = {Alexandria, Virginia},
pages = {141--151},
numpages = {11},
url = {http://doi.acm.org/10.1145/3132402.3132414},
doi = {10.1145/3132402.3132414},
acmid = {3132414},
publisher = {ACM},
address = {New York, NY, USA},
}Downloads
1710_Hameed_Memsys [PDF]
Related Paths
Permalink
- Adilla Susungi, Norman A. Rink, Jeronimo Castrillon, Immo Huismann, Albert Cohen, Claude Tadonki, Jörg Stiller, Jochen Fröhlich, "Towards Compositional and Generative Tensor Optimizations", Proceedings of 16th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE'17), ACM, pp. 169–175, New York, NY, USA, Oct 2017. [doi] [Bibtex & Downloads]
Towards Compositional and Generative Tensor Optimizations
×Reference
Adilla Susungi, Norman A. Rink, Jeronimo Castrillon, Immo Huismann, Albert Cohen, Claude Tadonki, Jörg Stiller, Jochen Fröhlich, "Towards Compositional and Generative Tensor Optimizations", Proceedings of 16th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE'17), ACM, pp. 169–175, New York, NY, USA, Oct 2017. [doi]
Bibtex
@InProceedings{rink_gpce17,
author = {Adilla Susungi and Norman A. Rink and Jeronimo Castrillon and Immo Huismann and Albert Cohen and Claude Tadonki and J{\"o}rg Stiller and Jochen Fr{\"o}hlich},
title = {Towards Compositional and Generative Tensor Optimizations},
booktitle = {Proceedings of 16th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE'17)},
series = {GPCE 2017},
year = {2017},
pages = {169--175},
month = oct,
isbn = {978-1-4503-5524-7},
location = {Vancouver, BC, Canada},
pages = {169--175},
numpages = {7},
url = {http://doi.acm.org/10.1145/3136040.3136050},
doi = {10.1145/3136040.3136050},
acmid = {3136050},
publisher = {ACM},
address = {New York, NY, USA},
}Downloads
1710_Rink_GPCE [PDF]
Related Paths
Permalink
- Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Factorizing the factorization \textendash a spectral-element solver for elliptic equations with linear operation count", In Journal of Computational Physics, Elsevier BV, vol. 346, pp. 437–448, Oct 2017. [doi] [Bibtex & Downloads]
Factorizing the factorization \textendash a spectral-element solver for elliptic equations with linear operation count
×Reference
Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Factorizing the factorization \textendash a spectral-element solver for elliptic equations with linear operation count", In Journal of Computational Physics, Elsevier BV, vol. 346, pp. 437–448, Oct 2017. [doi]
Bibtex
@article{Huismann_2017,
doi = {10.1016/j.jcp.2017.06.012},
url = {https://doi.org/10.1016%2Fj.jcp.2017.06.012},
year = 2017,
month = {oct},
publisher = {Elsevier {BV}},
volume = {346},
pages = {437--448},
author = {Immo Huismann and Jörg Stiller and Jochen Fröhlich},
title = {Factorizing the factorization {\textendash} a spectral-element solver for elliptic equations with linear operation count},
journal = {Journal of Computational Physics}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sven Karol, Tobias Nett, Pietro Incardona, Nesrine Khouzami, Jeronimo Castrillon, Ivo F. Sbalzarini, "A Language and Development Environment for Parallel Particle Methods", Proceedings of the 5th International Conference on Particle-based Methods. Fundamentals and Applications PARTICLES 2017 (P. Wriggers and M. Bischoff and E. Oñate and D.R.J. Owen and T. Zohdi), Sep 2017. [Bibtex & Downloads]
A Language and Development Environment for Parallel Particle Methods
×Reference
Sven Karol, Tobias Nett, Pietro Incardona, Nesrine Khouzami, Jeronimo Castrillon, Ivo F. Sbalzarini, "A Language and Development Environment for Parallel Particle Methods", Proceedings of the 5th International Conference on Particle-based Methods. Fundamentals and Applications PARTICLES 2017 (P. Wriggers and M. Bischoff and E. Oñate and D.R.J. Owen and T. Zohdi), Sep 2017.
Bibtex
@InProceedings{karol_particles17,
author = {Sven Karol and Tobias Nett and Pietro Incardona and Nesrine Khouzami and Jeronimo Castrillon and Ivo F. Sbalzarini},
title = {A Language and Development Environment for Parallel Particle Methods},
booktitle = {Proceedings of the 5th International Conference on Particle-based Methods. Fundamentals and Applications PARTICLES 2017},
year = {2017},
editor = {P. Wriggers and M. Bischoff and E. O{\~n}ate and D.R.J. Owen and T. Zohdi},
url = {https://www.semanticscholar.org/paper/A-Language-and-Development-Environment-for-Paralle-Karol-Nett/2b79bd3836aeb8e2fb2a2b5d9949f9efb1bdfab7?tab=abstract},
month = sep,
}Downloads
1709_Karol_particles [PDF]
Related Paths
Biological Systems Path, Orchestration Path
Permalink
- Jeronimo Castrillon, Tei-Wei Kuo, Heike E. Riel, Matthias Lieber, "Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061)", In Dagstuhl Reports (Jerónimo Castrillón-Mazo and Tei-Wei Kuo and Heike E. Riel and Matthias Lieber), Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, vol. 7, no. 2, pp. 1–22, Dagstuhl, Germany, Aug 2017. [doi] [Bibtex & Downloads]
Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061)
×Reference
Jeronimo Castrillon, Tei-Wei Kuo, Heike E. Riel, Matthias Lieber, "Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061)", In Dagstuhl Reports (Jerónimo Castrillón-Mazo and Tei-Wei Kuo and Heike E. Riel and Matthias Lieber), Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, vol. 7, no. 2, pp. 1–22, Dagstuhl, Germany, Aug 2017. [doi]
Bibtex
@Article{castrillnmazo_et_al:DR:2017:7349,
author = {Jeronimo Castrillon and Tei-Wei Kuo and Heike E. Riel and Matthias Lieber},
title = ,
journal = {Dagstuhl Reports},
year = {2017},
volume = {7},
number = {2},
month = aug,
pages = {1--22},
address = {Dagstuhl, Germany},
annote = {Keywords: 3D integration, compilers, emerging post-CMOS circuit materials and technologies, hardware/software co-design, heterogeneous hardware, nanoelectronics},
doi = {10.4230/DagRep.7.2.1},
editor = {Jer{\'o}nimo Castrill{\'o}n-Mazo and Tei-Wei Kuo and Heike E. Riel and Matthias Lieber},
issn = {2192-5283},
publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
url = {http://drops.dagstuhl.de/opus/volltexte/2017/7349},
urn = {urn:nbn:de:0030-drops-73499}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Andrés Goens, Sergio Siccha, Jeronimo Castrillon, "Symmetry in Software Synthesis", In ACM Transactions on Architecture and Code Optimization (TACO),, ACM, vol. 14, no. 2, pp. 20:1–20:26, New York, NY, USA, Jul 2017. [doi] [Bibtex & Downloads]
Symmetry in Software Synthesis
×Reference
Andrés Goens, Sergio Siccha, Jeronimo Castrillon, "Symmetry in Software Synthesis", In ACM Transactions on Architecture and Code Optimization (TACO),, ACM, vol. 14, no. 2, pp. 20:1–20:26, New York, NY, USA, Jul 2017. [doi]
Abstract
With the surge of multi- and manycores, much research has focused on algorithms for mapping and scheduling on these complex platforms. Large classes of these algorithms face scalability problems. This is why diverse methods are commonly used for reducing the search space. While most such approaches leverage the inherent symmetry of architectures and applications, they do it in a problem-specific and intuitive way. However, intuitive approaches become impractical with growing hardware complexity, like Network-on-Chip interconnect or heterogeneous cores. In this paper, we present a formal framework that can determine the inherent symmetry of architectures and applications algorithmically and leverage these for problems in software synthesis. Our approach is based on the mathematical theory of groups and a generalization called inverse semigroups. We evaluate our approach in two state-of-the-art mapping frameworks. Even for the platforms with a handful of cores of today and moderate-size benchmarks, our approach consistently yields reductions of the overall execution time of algorithms, accelerating them by a factor up to 10 in our experiments, or improving the quality of the results.
Bibtex
@article{goens_taco17symmetry,
author = {Goens, Andr{\'e}s and Siccha, Sergio and Castrillon, Jeronimo},
title = {Symmetry in Software Synthesis},
journal = {ACM Transactions on Architecture and Code Optimization (TACO),},
issue_date = {July 2017},
volume = {14},
number = {2},
month = jul,
year = {2017},
issn = {1544-3566},
pages = {20:1--20:26},
articleno = {20},
numpages = {26},
url = {http://doi.acm.org/10.1145/3095747},
doi = {10.1145/3095747},
acmid = {3095747},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {Scalability, automation, clusters, design-space exploration, group theory, heterogeneous, inverse-semigroups, mapping, metaheuristics, network-on-chip, symmetry},
eprint = "arXiv:1704.06623",
abstract = {With the surge of multi- and manycores, much research has focused on algorithms for mapping and scheduling on these complex platforms. Large classes of these algorithms face scalability problems. This is why diverse methods are commonly used for reducing the search space. While most such approaches leverage the inherent symmetry of architectures and applications, they do it in a problem-specific and intuitive way. However, intuitive approaches become impractical with growing hardware complexity, like Network-on-Chip interconnect or heterogeneous cores. In this paper, we present a formal framework that can determine the inherent symmetry of architectures and applications algorithmically and leverage these for problems in software synthesis. Our approach is based on the mathematical theory of groups and a generalization called inverse semigroups. We evaluate our approach in two state-of-the-art mapping frameworks. Even for the platforms with a handful of cores of today and moderate-size benchmarks, our approach consistently yields reductions of the overall execution time of algorithms, accelerating them by a factor up to 10 in our experiments, or improving the quality of the results.}
}Downloads
1704_Goens_TACO-arxiv [PDF]
Related Paths
Permalink
- Christian Menard, Matthias Jung, Jeronimo Castrillon, Norbert Wehn, "System Simulation with gem5 and SystemC: The Keystone for Full Interoperability", Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), pp. 62–69, Jul 2017. [doi] [Bibtex & Downloads]
System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
×Reference
Christian Menard, Matthias Jung, Jeronimo Castrillon, Norbert Wehn, "System Simulation with gem5 and SystemC: The Keystone for Full Interoperability", Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), pp. 62–69, Jul 2017. [doi]
Abstract
SystemC TLM based virtual prototypes have become the main tool in industry and research for concurrent hardware and software development, as well as hardware design space exploration. However, there exists a lack of accurate, free, changeable and realistic SystemC models of modern CPUs. Therefore, many researchers use the cycle accurate open source system simulator gem5, which has been developed in parallel to the SystemC standard. In this paper we present a coupling of gem5 with SystemC that offers full interoperability between both simulation frameworks, and therefore enables a huge set of possibilities for system level design space exploration. Furthermore, we show that the coupling itself only induces a relatively small overhead to the total execution time of the simulation.
Bibtex
@InProceedings{menard_samos17,
author = {Christian Menard and Matthias Jung and Jeronimo Castrillon and Norbert Wehn},
title = {System Simulation with gem5 and SystemC: The Keystone for Full Interoperability},
booktitle = {Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
year = {2017},
month = jul,
location = {Pythagorion, Greece},
pages = {62--69},
organization = {IEEE},
doi = {10.1109/SAMOS.2017.8344612},
url = {https://ieeexplore.ieee.org/document/8344612/},
isbn = {978-1-5386-3437-0},
abstract = {SystemC TLM based virtual prototypes have become the main tool in industry and research for concurrent hardware and software development, as well as hardware design space exploration. However, there exists a lack of accurate, free, changeable and realistic SystemC models of modern CPUs. Therefore, many researchers use the cycle accurate open source system simulator gem5, which has been developed in parallel to the SystemC standard. In this paper we present a coupling of gem5 with SystemC that offers full interoperability between both simulation frameworks, and therefore enables a huge set of possibilities for system level design space exploration. Furthermore, we show that the coupling itself only induces a relatively small overhead to the total execution time of the simulation.},
}Downloads
1707_Menard_SAMOS [PDF]
Related Paths
Permalink
- Andrés Goens, Robert Khasanov, Marcus Hähnel, Till Smejkal, Hermann Härtig, Jeronimo Castrillon, "TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings", Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES'17), ACM, pp. 11–20, New York, NY, USA, Jun 2017. [doi] [Bibtex & Downloads]
TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings
×Reference
Andrés Goens, Robert Khasanov, Marcus Hähnel, Till Smejkal, Hermann Härtig, Jeronimo Castrillon, "TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings", Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES'17), ACM, pp. 11–20, New York, NY, USA, Jun 2017. [doi]
Bibtex
@InProceedings{goens_scopes17,
author = {Andr\'{e}s Goens and Robert Khasanov and Marcus H{\"a}hnel and Till Smejkal and Hermann H{\"a}rtig and Jeronimo Castrillon},
title = {TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings},
booktitle = {Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES'17)},
year = {2017},
month = jun,
series = {SCOPES '17},
isbn = {978-1-4503-5039-6},
location = {Sankt Goar, Germany},
pages = {11--20},
numpages = {10},
url = {http://doi.acm.org/10.1145/3078659.3078663},
doi = {10.1145/3078659.3078663},
acmid = {3078663},
publisher = {ACM},
address = {New York, NY, USA}
}Downloads
1706_Goens_SCOPES [PDF]
Related Paths
Permalink
- Gerald Hempel, Andrés Goens, Josefine Asmus, Jeronimo Castrillon, Ivo F. Sbalzarini, "Robust Mapping of Process Networks to Many-Core Systems Using Bio-Inspired Design Centering", Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES '17), ACM, pp. 21–30, New York, NY, USA, Jun 2017. [doi] [Bibtex & Downloads]
Robust Mapping of Process Networks to Many-Core Systems Using Bio-Inspired Design Centering
×Reference
Gerald Hempel, Andrés Goens, Josefine Asmus, Jeronimo Castrillon, Ivo F. Sbalzarini, "Robust Mapping of Process Networks to Many-Core Systems Using Bio-Inspired Design Centering", Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES '17), ACM, pp. 21–30, New York, NY, USA, Jun 2017. [doi]
Bibtex
@InProceedings{hempel_scopes17,
author = {Gerald Hempel and Andr\'{e}s Goens and Josefine Asmus and Jeronimo Castrillon and Ivo F. Sbalzarini},
title = {Robust Mapping of Process Networks to Many-Core Systems Using Bio-Inspired Design Centering},
booktitle = {Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES '17)},
year = {2017},
series = {SCOPES '17},
pages = {21--30},
address = {New York, NY, USA},
month = jun,
publisher = {ACM},
acmid = {3078667},
doi = {10.1145/3078659.3078667},
isbn = {978-1-4503-5039-6},
location = {Sankt Goar, Germany},
numpages = {10},
url = {http://doi.acm.org/10.1145/3078659.3078667}
}Downloads
1706_Hempel_SCOPES [PDF]
Related Paths
Biological Systems Path, Orchestration Path
Permalink
- Norman A. Rink, Jeronimo Castrillon, "Extending a Compiler Backend for Complete Memory Error Detection", In Proceeding: Lecture Notes in Informatics: Automotive - Safety & Security 2017 (Peter Dencker and Herbert Klenk and Hubert Kelle and Erhard Plödereder), pp. 61–74, May 2017. (Best paper award) [Bibtex & Downloads]
Extending a Compiler Backend for Complete Memory Error Detection
×Reference
Norman A. Rink, Jeronimo Castrillon, "Extending a Compiler Backend for Complete Memory Error Detection", In Proceeding: Lecture Notes in Informatics: Automotive - Safety & Security 2017 (Peter Dencker and Herbert Klenk and Hubert Kelle and Erhard Plödereder), pp. 61–74, May 2017. (Best paper award)
Abstract
Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to faults. Applications can be protected against errors resulting from faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to intermediate program representations are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, the compiler backend may introduce additional memory accesses. This report presents an extended compiler backend that protects these accesses against faults in the memory system. It is demonstrated that this enables the detection of all single bit flips in memory. On a subset of SPEC CINT2006 the runtime overhead caused by the extended backend amounts to 1.50x for the 32-bit processor architecture i386, and 1.13x for the 64-bit architecture x86 64.
Bibtex
@InProceedings{rink_automotive17,
author = {Norman A. Rink and Jeronimo Castrillon},
title = {Extending a Compiler Backend for Complete Memory Error Detection},
booktitle = {Lecture Notes in Informatics: Automotive - Safety \& Security 2017},
editor = {Peter Dencker and Herbert Klenk and Hubert Kelle and Erhard Pl{\"o}dereder},
year = {2017},
pages = {61--74},
month = may,
abstract = {Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to faults. Applications can be protected against errors resulting from faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to intermediate program representations are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, the compiler backend may introduce additional memory accesses. This report presents an extended compiler backend that protects these accesses against faults in the memory system. It is demonstrated that this enables the detection of all single bit flips in memory. On a subset of SPEC CINT2006 the runtime overhead caused by the extended backend amounts to 1.50x for the 32-bit processor architecture i386, and 1.13x for the 64-bit architecture x86 64.},
file = {:/Users/jeronimocastrillon/Documents/Academic/mypapers/1705_rink_automotive.pdf:PDF},
isbn = {978-3-88579-663-3},
issn = {1617-5468},
url = {https://dl.gi.de/bitstream/handle/20.500.12116/147/paper04.pdf?sequence=1&isAllowed=y},
}Downloads
1705_rink_automotive [PDF]
Related Paths
Orchestration Path, Resilience Path
Permalink
- Norman A. Rink, Jeronimo Castrillon, "Trading Fault Tolerance for Performance in AN Encoding", Proceedings of the ACM International Conference on Computing Frontiers (CF'17), ACM, pp. 183–190, New York, NY, USA, May 2017. [doi] [Bibtex & Downloads]
Trading Fault Tolerance for Performance in AN Encoding
×Reference
Norman A. Rink, Jeronimo Castrillon, "Trading Fault Tolerance for Performance in AN Encoding", Proceedings of the ACM International Conference on Computing Frontiers (CF'17), ACM, pp. 183–190, New York, NY, USA, May 2017. [doi]
Bibtex
@InProceedings{rink_cf17,
author = {Norman A. Rink and Jeronimo Castrillon},
title = {Trading Fault Tolerance for Performance in {AN} Encoding},
booktitle = {Proceedings of the ACM International Conference on Computing Frontiers (CF'17)},
year = {2017},
isbn = {978-1-4503-4487-6},
location = {Siena, Italy},
pages = {183--190},
numpages = {8},
url = {http://doi.acm.org/10.1145/3075564.3075565},
doi = {10.1145/3075564.3075565},
acmid = {3075565},
publisher = {ACM},
address = {New York, NY, USA},
month = may,
}Downloads
1705_Rink_cf [PDF]
Related Paths
Orchestration Path, Resilience Path
Permalink
- Hasna Bouraoui, Chadlia Jerad, Anupam Chattopadhyay, Nejib Ben Hadj-Alouane, "Hardware Architectures for Embedded Speaker Recognition Applications", In ACM Transactions on Embedded Computing Systems, Association for Computing Machinery (ACM), vol. 16, no. 3, pp. 1–28, Apr 2017. [doi] [Bibtex & Downloads]
Hardware Architectures for Embedded Speaker Recognition Applications
×Reference
Hasna Bouraoui, Chadlia Jerad, Anupam Chattopadhyay, Nejib Ben Hadj-Alouane, "Hardware Architectures for Embedded Speaker Recognition Applications", In ACM Transactions on Embedded Computing Systems, Association for Computing Machinery (ACM), vol. 16, no. 3, pp. 1–28, Apr 2017. [doi]
Bibtex
@article{Bouraoui_2017,
doi = {10.1145/2975161},
url = {https://doi.org/10.1145%2F2975161},
year = 2017,
month = {apr},
publisher = {Association for Computing Machinery ({ACM})},
volume = {16},
number = {3},
pages = {1--28},
author = {Hasna Bouraoui and Chadlia Jerad and Anupam Chattopadhyay and Nejib Ben Hadj-Alouane},
title = {Hardware Architectures for Embedded Speaker Recognition Applications},
journal = {{ACM} Transactions on Embedded Computing Systems}
}Downloads
1704_Bouraoui_TECS [PDF]
Related Paths
Permalink
- Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]
Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits
×Reference
Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.
Bibtex
@InProceedings{raitza2017date,
author = {Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick},
title = {Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits},
booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
year = {2017},
month = {March},
organization = {IEEE}
}Downloads
date-2017-michael [PDF]
Related Paths
Permalink
- Fazal Hameed, Jeronimo Castrillon, "Rethinking On-chip DRAM Cache for Simultaneous Performance and Energy Optimization", Proceedings of the 2017 Design, Automation and Test in Europe conference (DATE), EDA Consortium, pp. 362–367, Mar 2017. [doi] [Bibtex & Downloads]
Rethinking On-chip DRAM Cache for Simultaneous Performance and Energy Optimization
×Reference
Fazal Hameed, Jeronimo Castrillon, "Rethinking On-chip DRAM Cache for Simultaneous Performance and Energy Optimization", Proceedings of the 2017 Design, Automation and Test in Europe conference (DATE), EDA Consortium, pp. 362–367, Mar 2017. [doi]
Abstract
State-of-the-art DRAM cache employs a small Tag-Cache and its performance is dependent upon two important parameters namely bank-level-parallelism and Tag-Cache hit rate. These parameters depend upon the row buffer organization. Recently, it has been shown that a small row buffer organization delivers better performance via improved bank-level-parallelism than the traditional large row buffer organization along with energy benefits. However, small row buffers do not fully exploit the temporal locality of tag accesses, leading to reduced Tag- Cache hit rates. As a result, the DRAM cache needs to be re-designed for small row buffer organization to achieve additional performance benefits. In this paper, we propose a novel tag-store mechanism that improves the Tag-Cache hit rate by 70% compared to existing DRAM tag-store mechanisms employing small row buffer organization. In addition, we enhance the DRAM cache controller with novel policies that take into account the locality characteristics of cache accesses. We evaluate our novel tag-store mechanism and controller policies in an 8-core system running the SPEC2006 benchmark and compare their performance and energy consumption against recent proposals. Our architecture improves the average performance by 21.2% and 11.4% respectively compared to large and small row buffer organizations via simultaneously improving both parameters. Compared to DRAM cache with large row buffer organization, we report an energy improvement of 62%.
Bibtex
@InProceedings{hameed_date17,
author = {Fazal Hameed and Jeronimo Castrillon},
title = {Rethinking On-chip DRAM Cache for Simultaneous Performance and Energy Optimization},
booktitle = {Proceedings of the 2017 Design, Automation and Test in Europe conference (DATE)},
year = {2017},
series = {DATE '17},
pages = {362--367},
month = mar,
publisher = {EDA Consortium},
abstract = {State-of-the-art DRAM cache employs a small Tag-Cache and its performance is dependent upon two important parameters namely bank-level-parallelism and Tag-Cache hit rate. These parameters depend upon the row buffer organization. Recently, it has been shown that a small row buffer organization delivers better performance via improved bank-level-parallelism than the traditional large row buffer organization along with energy benefits. However, small row buffers do not fully exploit the temporal locality of tag accesses, leading to reduced Tag- Cache hit rates. As a result, the DRAM cache needs to be re-designed for small row buffer organization to achieve additional performance benefits. In this paper, we propose a novel tag-store mechanism that improves the Tag-Cache hit rate by 70\% compared to existing DRAM tag-store mechanisms employing small row buffer organization. In addition, we enhance the DRAM cache controller with novel policies that take into account the locality characteristics of cache accesses. We evaluate our novel tag-store mechanism and controller policies in an 8-core system running the SPEC2006 benchmark and compare their performance and energy consumption against recent proposals. Our architecture improves the average performance by 21.2\% and 11.4\% respectively compared to large and small row buffer organizations via simultaneously improving both parameters. Compared to DRAM cache with large row buffer organization, we report an energy improvement of 62\%.},
isbn = {978-3-9815370-8-6},
doi={10.23919/DATE.2017.7927017},
url = {http://ieeexplore.ieee.org/document/7927017/},
location = {Lausanne, Switzerland}
}Downloads
1703_Hameed_DATE [PDF]
Related Paths
Permalink
- Norman A. Rink, Jeronimo Castrillon, "flexMEDiC: flexible Memory Error Detection by Combined data encoding and duplication", Proceedings of the 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with DATE 2017, pp. 15–22, Mar 2017. [Bibtex & Downloads]
flexMEDiC: flexible Memory Error Detection by Combined data encoding and duplication
×Reference
Norman A. Rink, Jeronimo Castrillon, "flexMEDiC: flexible Memory Error Detection by Combined data encoding and duplication", Proceedings of the 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with DATE 2017, pp. 15–22, Mar 2017.
Abstract
Errors in memory are known to be a major cause of system failures. Moreover, it has recently been found that single-error correcting, double-error detecting (SECDED) codes, which are widely used in ECC memory modules, are incapable of handling large fractions of errors that occur in practice. This calls for more powerful error detection measures. However, the higher the number of bit flips that can still be detected as an error, the larger the memory overhead. Cost considerations and the varying needs for reliability of different applications may not always warrant laying down extra hardware to accommodate overheads. Software-implemented error detection offers a flexible alternative. In this work we propose the software-implemented flexMEDiC scheme for detecting errors in the memory system, including main memory, on-chip caches, and load-store queues. It is shown that single and double bit flips are detected by flexMEDiC, and evidence is given that suggests that up to five bit flips within a single data word can still be detected as errors. The average runtime overhead incurred by flexMEDiC is 1.55x.
Bibtex
@InProceedings{rees:2017,
author = {Norman A. Rink and Jeronimo Castrillon},
title = {{flexMEDiC}: flexible {M}emory {E}rror {D}etection by Combined data encoding and duplication},
booktitle = {Proceedings of the 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with DATE 2017},
year = {2017},
month = mar,
pages = {15--22},
abstract = {Errors in memory are known to be a major cause of system failures. Moreover, it has recently been found that single-error correcting, double-error detecting (SECDED) codes, which are widely used in ECC memory modules, are incapable of handling large fractions of errors that occur in practice. This calls for more powerful error detection measures. However, the higher the number of bit flips that can still be detected as an error, the larger the memory overhead. Cost considerations and the varying needs for reliability of different applications may not always warrant laying down extra hardware to accommodate overheads. Software-implemented error detection offers a flexible alternative. In this work we propose the software-implemented flexMEDiC scheme for detecting errors in the memory system, including main memory, on-chip caches, and load-store queues. It is shown that single and double bit flips are detected by flexMEDiC, and evidence is given that suggests that up to five bit flips within a single data word can still be detected as errors. The average runtime overhead incurred by flexMEDiC is 1.55x.},
}Downloads
1703_Rink_REES [PDF]
Related Paths
Permalink
- Andrés Goens, Jeronimo Castrillon, "Optimizing for Data-Parallelism in Kahn Process Networks", In Proceeding: ACM SRC at International Symposium on
Code Generationand Optimization (CGO), Feb 2017. [Bibtex & Downloads]
Optimizing for Data-Parallelism in Kahn Process Networks
×Reference
Andrés Goens, Jeronimo Castrillon, "Optimizing for Data-Parallelism in Kahn Process Networks", In Proceeding: ACM SRC at International Symposium on Code Generationand Optimization (CGO), Feb 2017.
Bibtex
@inproceedings{goens17cgo,
author = {Andr\'{e}s Goens and Jeronimo Castrillon},
title = {Optimizing for Data-Parallelism in Kahn Process Networks},
year = {2017},
month = feb,
booktitle= {ACM SRC at International Symposium on
Code Generationand Optimization (CGO)},
location = {Austin, TX, USA},
}Downloads
1701_Goens_SRCCGO [PDF]
Related Paths
Permalink
- Jeronimo Castrillon, "On Mapping to Multi/Manycores", In 10th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2017), held in conjunction with the 12th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) (invited talk), Jan 2017. [Bibtex & Downloads]
On Mapping to Multi/Manycores
×Reference
Jeronimo Castrillon, "On Mapping to Multi/Manycores", In 10th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2017), held in conjunction with the 12th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) (invited talk), Jan 2017.
Bibtex
@Misc{castrillon2017multiprog,
author = {Castrillon, Jeronimo},
title = {On Mapping to Multi/Manycores},
howpublished = {10th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2017), held in conjunction with the 12th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) (invited talk)},
month = jan,
year = {2017},
location = {Stockholm, Sweden}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Jeronimo Castrillon, "Flexible and Scalable Dataflow Programming for Manycores", In Tutorial for heterogeneous multicore design automation: current and future, held in conjunction with the 12th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) (invited talk), Jan 2017. [Bibtex & Downloads]
Flexible and Scalable Dataflow Programming for Manycores
×Reference
Jeronimo Castrillon, "Flexible and Scalable Dataflow Programming for Manycores", In Tutorial for heterogeneous multicore design automation: current and future, held in conjunction with the 12th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) (invited talk), Jan 2017.
Bibtex
@Misc{castrillon2017hipeactut,
author = {Castrillon, Jeronimo},
title = {Flexible and Scalable Dataflow Programming for Manycores},
howpublished = {Tutorial for heterogeneous multicore design automation: current and future, held in conjunction with the 12th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) (invited talk)},
month = jan,
year = {2017},
location = {Stockholm, Sweden}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Rui Santos, Shyamsundar Venkataraman, Akash Kumar, "Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices", In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017. [Bibtex & Downloads]
Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices
×Reference
Rui Santos, Shyamsundar Venkataraman, Akash Kumar, "Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices", In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.
Bibtex
@article{rui-todaes-2017,
title = {Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices},
journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
year = {2017},
author = {Rui Santos and Shyamsundar Venkataraman and Akash Kumar}
}Downloads
todaes-2017-scrubbing [PDF]
Related Paths
Permalink
- Matthias Lieber, Wolfgang E. Nagel, "Highly scalable SFC-based dynamic load balancing and its application to atmospheric modeling", In Future Generation Computer Systems, 2017. [doi] [Bibtex & Downloads]
Highly scalable SFC-based dynamic load balancing and its application to atmospheric modeling
×Reference
Matthias Lieber, Wolfgang E. Nagel, "Highly scalable SFC-based dynamic load balancing and its application to atmospheric modeling", In Future Generation Computer Systems, 2017. [doi]
Bibtex
@ARTICLE{lieber:2017:a,
author = {Lieber, Matthias and Nagel, Wolfgang E.},
title = {Highly scalable SFC-based dynamic load balancing and its application to atmospheric modeling},
journal = {Future Generation Computer Systems},
year = {2017},
note = {in press},
doi = {10.1016/j.future.2017.04.042}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Immo Huismann, Matthias Lieber, Jörg Stiller, Jochen Fröhlich, "Load Balancing for CPU-GPU Coupling in Computational Fluid Dynamics" (to appear), In Proceeding: Proc. of PPAM 2017, 2017. [Bibtex & Downloads]
Load Balancing for CPU-GPU Coupling in Computational Fluid Dynamics
×Reference
Immo Huismann, Matthias Lieber, Jörg Stiller, Jochen Fröhlich, "Load Balancing for CPU-GPU Coupling in Computational Fluid Dynamics" (to appear), In Proceeding: Proc. of PPAM 2017, 2017.
Bibtex
@INPROCEEDINGS{huismann:2017:a,
author = {Huismann, Immo and Lieber, Matthias and Stiller, J{\"{o}}rg and Fr{\"{o}}hlich, Jochen},
title = {Load Balancing for CPU-GPU Coupling in Computational Fluid Dynamics},
booktitle = {Proc. of PPAM 2017},
series = {LNCS},
year = {2017}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Factorizing the factorization – a spectral-element solver for elliptic equations with linear operation count" , In Journal of Computational Physics, vol. 346, pp. 437-448, 2017. [doi] [Bibtex & Downloads]
Factorizing the factorization – a spectral-element solver for elliptic equations with linear operation count
×Reference
Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Factorizing the factorization – a spectral-element solver for elliptic equations with linear operation count" , In Journal of Computational Physics, vol. 346, pp. 437-448, 2017. [doi]
Bibtex
@article{huismann_2017_condensation,
title = Factorizing the factorization – a spectral-element solver for
elliptic equations with linear operation count,
journal = "Journal of Computational Physics",
volume = "346",
number = "",
pages = "437 - 448",
year = "2017",
note = "",
issn = "0021-9991",
doi = "http://dx.doi.org/10.1016/j.jcp.2017.06.012",
url = "http://www.sciencedirect.com/science/article/pii/S0021999117304576",
author = "Immo Huismann and Jörg Stiller and Jochen Fröhlich",
keywords = "Spectral-element method",
keywords = "Elliptic equations",
keywords = "Substructuring",
keywords = "Static condensation"
}
Downloads
No Downloads available for this publication
Related Paths
Permalink
- David Müller andSalomon Sickert, "LTL to Deterministic Emerson-Lei Automata", In Proceeding: Proc. of the 8th International Symposium on Games, Automata, Logics, and Formal Verification (GandALF), 2017. [Bibtex & Downloads]
LTL to Deterministic Emerson-Lei Automata
×Reference
David Müller andSalomon Sickert, "LTL to Deterministic Emerson-Lei Automata", In Proceeding: Proc. of the 8th International Symposium on Games, Automata, Logics, and Formal Verification (GandALF), 2017.
Bibtex
@inproceedings{MS17,
author = {David M{\"u}ller and
Salomon Sickert},
title = {LTL to Deterministic Emerson-Lei Automata},
booktitle = {Proc. of the 8th International Symposium on Games, Automata, Logics, and Formal Verification (GandALF)},
year = {2017},
note = {Accepted for publication},
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Resilience Path
Permalink
- Lisa Hutschenreiter, Christel Baier, Joachim Klein, "Parametric Markov Chains: PCTL Complexity and Fraction-free Gaussian Elimination", In Proceeding: Proc. of the 8th International Symposium on Games, Automata, Logics, and Formal Verification (GandALF), 2017. [Bibtex & Downloads]
Parametric Markov Chains: PCTL Complexity and Fraction-free Gaussian Elimination
×Reference
Lisa Hutschenreiter, Christel Baier, Joachim Klein, "Parametric Markov Chains: PCTL Complexity and Fraction-free Gaussian Elimination", In Proceeding: Proc. of the 8th International Symposium on Games, Automata, Logics, and Formal Verification (GandALF), 2017.
Bibtex
@inproceedings{HBK17,
author = {Lisa Hutschenreiter and Christel Baier and Joachim Klein},
title = {Parametric Markov Chains: {PCTL} Complexity and Fraction-free {Gaussian} Elimination},
booktitle = {Proc. of the 8th International Symposium on Games, Automata, Logics, and Formal Verification (GandALF)},
year = {2017},
note = {Accepted for publication},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Philipp Chrszon, Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "ProFeat: Feature-oriented Engineering for Family-based Probabilistic Model Checking", In Formal Aspects of Computing, 2017. [Bibtex & Downloads]
ProFeat: Feature-oriented Engineering for Family-based Probabilistic Model Checking
×Reference
Philipp Chrszon, Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "ProFeat: Feature-oriented Engineering for Family-based Probabilistic Model Checking", In Formal Aspects of Computing, 2017.
Bibtex
@article{CDKB17,
author = {Philipp Chrszon and Clemens Dubslaff and Sascha Kl{\"u}ppelholz and Christel Baier},
title = {{ProFeat}: Feature-oriented Engineering for Family-based Probabilistic Model Checking},
journal = {Formal Aspects of Computing},
year = {2017},
note = {Accepted for publication},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Linda Leuschner, Martin Küttler, Tobias Stumpf, Christel Baier, Hermann Härtig, Sascha Klüppelholz, "Towards Automated Configuration of Systems with Non-Functional Constraints", Proceedings of the 16th Workshop on Hot Topics in Operating Systems (HotOS), 2017. [Bibtex & Downloads]
Towards Automated Configuration of Systems with Non-Functional Constraints
×Reference
Linda Leuschner, Martin Küttler, Tobias Stumpf, Christel Baier, Hermann Härtig, Sascha Klüppelholz, "Towards Automated Configuration of Systems with Non-Functional Constraints", Proceedings of the 16th Workshop on Hot Topics in Operating Systems (HotOS), 2017.
Bibtex
@inproceedings{LKSBHS17,
author = {Linda Leuschner and Martin K{\"u}ttler and Tobias Stumpf and Christel Baier and Hermann H{\"a}rtig and Sascha Kl{\"u}ppelholz},
title = {Towards Automated Configuration of Systems with Non-Functional Constraints},
booktitle = {Proceedings of the 16th Workshop on Hot Topics in Operating Systems (HotOS)},
year = {2017},
note = {Accepted for publication},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Steffen Märcker, Christel Baier, Joachim Klein, Sascha Klüppelholz, "Computing Conditional Probabilities: Implementation and Evaluation", In Proceeding: Proc. of the 15th International Conference on Software Engineering and Formal Methods (SEFM), 2017. [Bibtex & Downloads]
Computing Conditional Probabilities: Implementation and Evaluation
×Reference
Steffen Märcker, Christel Baier, Joachim Klein, Sascha Klüppelholz, "Computing Conditional Probabilities: Implementation and Evaluation", In Proceeding: Proc. of the 15th International Conference on Software Engineering and Formal Methods (SEFM), 2017.
Bibtex
@inproceedings{MBKK17,
author = {Steffen M{\"a}rcker and Christel Baier and Joachim Klein and Sascha Kl{\"u}ppelholz},
title = {Computing Conditional Probabilities: Implementation and Evaluation},
booktitle = {Proc. of the 15th International Conference on Software Engineering and Formal Methods (SEFM)},
year = {2017},
note = {Accepted for publication},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Clemens Dubslaff, \v Luboš Koren\v ciak, Antonín Ku\v cera, Vojt\v ech \v Rehák, "Mean-Payoff Optimization in Continuous-Time Markov Chains with Parametric Alarms", In Proceeding: Proc. of the 14th International Conference on Quantitative Evaluation of Systems (QEST), 2017. [Bibtex & Downloads]
Mean-Payoff Optimization in Continuous-Time Markov Chains with Parametric Alarms
×Reference
Christel Baier, Clemens Dubslaff, \v Luboš Koren\v ciak, Antonín Ku\v cera, Vojt\v ech \v Rehák, "Mean-Payoff Optimization in Continuous-Time Markov Chains with Parametric Alarms", In Proceeding: Proc. of the 14th International Conference on Quantitative Evaluation of Systems (QEST), 2017.
Bibtex
@inproceedings{BDKKR17a,
author = {Christel Baier and Clemens Dubslaff and {\v L}ubo{\v s} Koren{\v c}iak and Anton{\'i}n Ku{\v c}era and Vojt{\v e}ch {\v R}eh{\'a}k},
title = {Mean-Payoff Optimization in Continuous-Time {Markov} Chains with Parametric Alarms},
booktitle = {Proc. of the 14th International Conference on Quantitative Evaluation of Systems (QEST)},
year = 2017,
note = {Accepted for publication},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Clemens Dubslaff, Antonín Ku\vcera, Vojt\vech \vRehák, others, "Synthesis of optimal resilient control strategies", In Proceeding: International Symposium on Automated Technology for Verification and Analysis, pp. 417–434, 2017. [Bibtex & Downloads]
Synthesis of optimal resilient control strategies
×Reference
Christel Baier, Clemens Dubslaff, Antonín Ku\vcera, Vojt\vech \vRehák, others, "Synthesis of optimal resilient control strategies", In Proceeding: International Symposium on Automated Technology for Verification and Analysis, pp. 417–434, 2017.
Bibtex
@inproceedings{baier2017synthesis,
title={Synthesis of optimal resilient control strategies},
author={Baier, Christel and Dubslaff, Clemens and Ku{\v{c}}era, Anton{\'\i}n and {\v{R}}eh{\'a}k, Vojt{\v{e}}ch and others},
booktitle={International Symposium on Automated Technology for Verification and Analysis},
pages={417--434},
year={2017},
organization={Springer}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Joachim Klein, Linda Leuschner, David Parker, Sascha Wunderlich, "Ensuring the Reliability of Your Model Checker: Interval Iteration for Markov Decision Processes", In Proceeding: Proc. of the 29th International Conference on Computer Aided Verification (CAV), Part I, Springer, vol. 10426, pp. 160–180, 2017. [Bibtex & Downloads]
Ensuring the Reliability of Your Model Checker: Interval Iteration for Markov Decision Processes
×Reference
Christel Baier, Joachim Klein, Linda Leuschner, David Parker, Sascha Wunderlich, "Ensuring the Reliability of Your Model Checker: Interval Iteration for Markov Decision Processes", In Proceeding: Proc. of the 29th International Conference on Computer Aided Verification (CAV), Part I, Springer, vol. 10426, pp. 160–180, 2017.
Bibtex
@inproceedings{BKLPW17,
author = {Christel Baier and Joachim Klein and Linda Leuschner and David Parker and Sascha Wunderlich},
title = {Ensuring the Reliability of Your Model Checker: Interval Iteration for Markov Decision Processes},
booktitle = {Proc. of the 29th International Conference on Computer Aided Verification (CAV), Part {I}},
series = {Lecture Notes in Computer Science},
volume = {10426},
pages = {160--180},
publisher = {Springer},
year = {2017},
ee = {http://dx.doi.org/10.1007/978-3-319-63387-9_8},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Joachim Klein, Christel Baier, Philipp Chrszon, Marcus Daum, Clemens Dubslaff, Sascha Klüppelholz, Steffen Märcker, David Müller, "Advances in probabilistic model checking with PRISM: variable reordering, quantiles and weak deterministic Büchi automata", In International Journal on Software Tools for Technology Transfer, pp. 1–16, 2017. [Bibtex & Downloads]
Advances in probabilistic model checking with PRISM: variable reordering, quantiles and weak deterministic Büchi automata
×Reference
Joachim Klein, Christel Baier, Philipp Chrszon, Marcus Daum, Clemens Dubslaff, Sascha Klüppelholz, Steffen Märcker, David Müller, "Advances in probabilistic model checking with PRISM: variable reordering, quantiles and weak deterministic Büchi automata", In International Journal on Software Tools for Technology Transfer, pp. 1–16, 2017.
Bibtex
@article{KBCDDKMM17,
author = {Joachim Klein and Christel Baier and Philipp Chrszon and Marcus Daum and Clemens Dubslaff and Sascha Kl{\"u}ppelholz and Steffen M{\"a}rcker and David M{\"u}ller},
title = {Advances in probabilistic model checking with {PRISM}: variable reordering, quantiles and weak deterministic {B\"uchi} automata},
journal = {International Journal on Software Tools for Technology Transfer},
year = {2017},
pages = {1--16},
ee = {http://dx.doi.org/10.1007/s10009-017-0456-3},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Joachim Klein, Sascha Klüppelholz, Sascha Wunderlich, "Maximizing the Conditional Expected Reward for Reaching the Goal", In Proceeding: Proc. of the 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Part II, Springer, vol. 10206, pp. 269–285, 2017. [Bibtex & Downloads]
Maximizing the Conditional Expected Reward for Reaching the Goal
×Reference
Christel Baier, Joachim Klein, Sascha Klüppelholz, Sascha Wunderlich, "Maximizing the Conditional Expected Reward for Reaching the Goal", In Proceeding: Proc. of the 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Part II, Springer, vol. 10206, pp. 269–285, 2017.
Bibtex
@inproceedings{BKKW17,
author = {Christel Baier and Joachim Klein and Sascha Kl{\"u}ppelholz and Sascha Wunderlich},
title = {Maximizing the Conditional Expected Reward for Reaching the Goal},
booktitle = {Proc. of the 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Part {II}},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {10206},
pages = {269--285},
year = {2017},
ee = {http://dx.doi.org/10.1007/978-3-662-54580-5_16},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- David Carral, Irina Dragoste, Markus Krötzsch, "Restricted Chase (Non) Termination for Existential Rules with Disjunctions.", In Proceeding: IJCAI, pp. 922–928, 2017. [Bibtex & Downloads]
Restricted Chase (Non) Termination for Existential Rules with Disjunctions.
×Reference
David Carral, Irina Dragoste, Markus Krötzsch, "Restricted Chase (Non) Termination for Existential Rules with Disjunctions.", In Proceeding: IJCAI, pp. 922–928, 2017.
Bibtex
@inproceedings{carral2017restricted,
title={Restricted Chase (Non) Termination for Existential Rules with Disjunctions.},
author={Carral, David and Dragoste, Irina and Kr{\"o}tzsch, Markus},
booktitle={IJCAI},
pages={922--928},
year={2017}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas Augustin, Friedrich Pauls, Sadia Moriam, others, "A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications", Proceedings of the 54th Annual Design Automation Conference 2017, pp. 1–6, 2017. [Bibtex & Downloads]
A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications
×Reference
Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas Augustin, Friedrich Pauls, Sadia Moriam, others, "A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications", Proceedings of the 54th Annual Design Automation Conference 2017, pp. 1–6, 2017.
Bibtex
@inproceedings{haas2017heterogeneous,
title={A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications},
author={Haas, Sebastian and Seifert, Tobias and N{\"o}then, Benedikt and Scholze, Stefan and H{\"o}ppner, Sebastian and Dixius, Andreas and Adeva, Esther P{\'e}rez and Augustin, Thomas and Pauls, Friedrich and Moriam, Sadia and others},
booktitle={Proceedings of the 54th Annual Design Automation Conference 2017},
pages={1--6},
year={2017}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
2016
- Norman A. Rink, Jeronimo Castrillon, "Comprehensive Backend Support for Local Memory Fault Tolerance", Technical report, Technische Universität Dresden, pp. 11, Dec 2016. [Bibtex & Downloads]
Comprehensive Backend Support for Local Memory Fault Tolerance
×Reference
Norman A. Rink, Jeronimo Castrillon, "Comprehensive Backend Support for Local Memory Fault Tolerance", Technical report, Technische Universität Dresden, pp. 11, Dec 2016.
Bibtex
@TechReport{rink_techrep16,
author = {Norman A. Rink and Jeronimo Castrillon},
title = {Comprehensive Backend Support for Local Memory Fault Tolerance},
institution = {Technische Universit{\"a}t Dresden},
year = {2016},
month = dec,
issn = {1430-211X},
pages = {11},
url = {https://cfaed.tu-dresden.de/files/user/nrink/tech-report-ro.pdf}
}Downloads
tech-report-ro [PDF]
Related Paths
Permalink
- Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware", Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016. [Bibtex & Downloads]
The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware
×Reference
Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware", Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016.
Abstract
Future systems based on post-CMOS technologies,
will be wildly heterogeneous, with properties largely unknown today.,
This paper presents our design of a new hardware/software stack to address the,
challenge of preparing software development for such systems.,
It combines well-understood technologies from different areas, e.g., network-on-chips,
capability operating systems, flexible programming models and model checking.,
We describe our approach and provide details on key technologies.Bibtex
@InProceedings{voelp16_pmes,
author = {Marcus V{\"o}lp and Sascha Kl{\"u}ppelholz and Jeronimo Castrillon and Hermann H{\"a}rtig and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andres Goens and Sebastian Haas and Dirk Habich and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Wolfgang Lehner and Linda Leuschner and Matthias Lieber and Siqi Ling and Steffen M{\"a}rcker and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt},
title = {The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware},
booktitle = {Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16)},
year = {2016},
address = {Salt Lake City, USA},
month = nov,
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/1611_Voelp_PMES.pdf},
abstract = {Future systems based on post-CMOS technologies,
will be wildly heterogeneous, with properties largely unknown today.,
This paper presents our design of a new hardware/software stack to address the,
challenge of preparing software development for such systems.,
It combines well-understood technologies from different areas, e.g., network-on-chips,
capability operating systems, flexible programming models and model checking.,
We describe our approach and provide details on key technologies.},
}Downloads
1611_Voelp_PMES [PDF]
Related Paths
Permalink
- Christian Menard, Andrés Goens, Jeronimo Castrillon, "High-Level NoC Model for MPSoC Compilers", Proceedings of the IEEE Nordic Circuits and Systems Conference (NORCAS'16), pp. 1-6, Copenhagen, Denmark, Nov 2016. [doi] [Bibtex & Downloads]
High-Level NoC Model for MPSoC Compilers
×Reference
Christian Menard, Andrés Goens, Jeronimo Castrillon, "High-Level NoC Model for MPSoC Compilers", Proceedings of the IEEE Nordic Circuits and Systems Conference (NORCAS'16), pp. 1-6, Copenhagen, Denmark, Nov 2016. [doi]
Bibtex
@InProceedings{menard_norcas16,
author = {Christian Menard and Andr\'{e}s Goens and Jeronimo Castrillon},
title = {High-Level NoC Model for MPSoC Compilers},
booktitle = {Proceedings of the IEEE Nordic Circuits and Systems Conference (NORCAS'16)},
year = {2016},
pages={1-6},
doi = {10.1109/NORCHIP.2016.7792876},
series = {NORCAS},
address = {Copenhagen, Denmark},
month = nov,
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/1611_Menard_NORCAS.pdf}
}Downloads
1611_Menard_NORCAS [PDF]
Related Paths
Permalink
- Nam Khanh Pham, Akash Kumar, Khin Mi Mi Aung, "Automatic framework to generate reconfigurable accelerators for option pricing applications", In Proceeding: International Conference on Reconfigurable Computing and FPGAs (ReConFig), Nov 2016. [Bibtex & Downloads]
Automatic framework to generate reconfigurable accelerators for option pricing applications
×Reference
Nam Khanh Pham, Akash Kumar, Khin Mi Mi Aung, "Automatic framework to generate reconfigurable accelerators for option pricing applications", In Proceeding: International Conference on Reconfigurable Computing and FPGAs (ReConFig), Nov 2016.
Bibtex
@InProceedings{Khanh-Reconfig-2016,
title = {Automatic framework to generate reconfigurable accelerators for option pricing applications},
Booktitle = {International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
year = {2016},
month={Nov},
author = {Nam Khanh Pham and Akash Kumar and Khin Mi Mi Aung}
}Downloads
ReConFig_2016 [PDF]
Related Paths
Permalink
- Andres Goens, Robert Khasanov, Jeronimo Castrillon, Simon Polstra, Andy Pimentel, "Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study", Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), pp. 281-288, Ecole Centrale de Lyon, Lyon, France, Sep 2016. [doi] [Bibtex & Downloads]
Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study
×Reference
Andres Goens, Robert Khasanov, Jeronimo Castrillon, Simon Polstra, Andy Pimentel, "Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study", Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), pp. 281-288, Ecole Centrale de Lyon, Lyon, France, Sep 2016. [doi]
Abstract
Software abstractions are crucial to effectively program heterogeneous Multi-Processor Systems on Chip (MPSoCs). Prime examples of such abstractions are Kahn Process Networks (KPNs) and execution traces. When modeling computation as a KPN, one of the key challenges is to obtain a good mapping, i.e., an assignment of logical computation and communication to physical resources. In this paper we compare two system-level frameworks for solving the mapping problem: Sesame and MAPS. These frameworks, while superficially similar, embody different approaches. Sesame, motivated by modeling and design-space exploration, uses evolutionary algorithms for mapping. MAPS, being a compiler framework, uses simple and fast heuristics instead. In this work we highlight the value of common abstractions, such as KPNs and traces, as a vehicle to enable comparisons between large independent frameworks. These types of comparisons are fundamental for advancing research in the area. At the same time, we illustrate how the lack of formalized models at the hardware level are an obstacle to achieving fair comparisons. Additionally, using a set of applications from the embedded systems domain, we observe that genetic algorithms tend to outperform heuristics by a factor between 1x and 5x, with notable exceptions. This performance comes at the cost of a longer computation time, between 0 and 2 orders of magnitude in our experiments.
Bibtex
@InProceedings{goen_mcsoc16,
author= {Andres Goens and Robert Khasanov and Jeronimo Castrillon and Simon Polstra and Andy Pimentel},
title= {Why Comparing System-level {MPSoC} Mapping Approaches is Difficult: a Case Study},
booktitle= {Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16)},
year= {2016},
address= {Ecole Centrale de Lyon, Lyon, France},
month= sep,
pages = {281-288},
doi = {10.1109/MCSoC.2016.48},
abstract = {Software abstractions are crucial to effectively program heterogeneous Multi-Processor Systems on Chip (MPSoCs). Prime examples of such abstractions are Kahn Process Networks (KPNs) and execution traces. When modeling computation as a KPN, one of the key challenges is to obtain a good mapping, i.e., an assignment of logical computation and communication to physical resources. In this paper we compare two system-level frameworks for solving the mapping problem: Sesame and MAPS. These frameworks, while superficially similar, embody different approaches. Sesame, motivated by modeling and design-space exploration, uses evolutionary algorithms for mapping. MAPS, being a compiler framework, uses simple and fast heuristics instead. In this work we highlight the value of common abstractions, such as KPNs and traces, as a vehicle to enable comparisons between large independent frameworks. These types of comparisons are fundamental for advancing research in the area. At the same time, we illustrate how the lack of formalized models at the hardware level are an obstacle to achieving fair comparisons. Additionally, using a set of applications from the embedded systems domain, we observe that genetic algorithms tend to outperform heuristics by a factor between 1x and 5x, with notable exceptions. This performance comes at the cost of a longer computation time, between 0 and 2 orders of magnitude in our experiments.},
days= {21},
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/1609_Goens_MCSoC.pdf}
}Downloads
1609_Goens_MCSoC [PDF]
Related Paths
Permalink
- Benjamin Schiller, Clemens Deusser, Jeronimo Castrillon, Thorsten Strufe, "Compile- and Run-time Approaches for the Selection of Efficient Data Structures for Dynamic Graph Analysis", In Journal of Applied Network Science, vol. 1, no. 9, pp. 1–22, Sep 2016. [doi] [Bibtex & Downloads]
Compile- and Run-time Approaches for the Selection of Efficient Data Structures for Dynamic Graph Analysis
×Reference
Benjamin Schiller, Clemens Deusser, Jeronimo Castrillon, Thorsten Strufe, "Compile- and Run-time Approaches for the Selection of Efficient Data Structures for Dynamic Graph Analysis", In Journal of Applied Network Science, vol. 1, no. 9, pp. 1–22, Sep 2016. [doi]
Bibtex
@Article{schiller16_jans,
author = {Benjamin Schiller and Clemens Deusser and Jeronimo Castrillon and Thorsten Strufe},
title = {Compile- and Run-time Approaches for the Selection of Efficient Data Structures for Dynamic Graph Analysis},
journal = {Journal of Applied Network Science},
year = {2016},
volume = {1},
number = {9},
pages = {1--22},
month = sep,
doi = {10.1007/s41109-016-0011-2},
url= {http://dynamic-networks.org/publications/papers/papers/gds-dynamic.pdf}
}Downloads
1607_Schiller_JANS [PDF]
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Andrés Goens, Jeronimo Castrillon, Maximilian Odendahl, Rainer Leupers, "An Optimal Allocation of Memory Buffers for Complex Multicore Platforms", In Journal of Systems Architecture, Elsevier, vol. 66-67, pp. 69–83, May 2016. [doi] [Bibtex & Downloads]
An Optimal Allocation of Memory Buffers for Complex Multicore Platforms
×Reference
Andrés Goens, Jeronimo Castrillon, Maximilian Odendahl, Rainer Leupers, "An Optimal Allocation of Memory Buffers for Complex Multicore Platforms", In Journal of Systems Architecture, Elsevier, vol. 66-67, pp. 69–83, May 2016. [doi]
Abstract
In deeply embedded heterogeneous multicores the allocation of data to memories is crucial for application performance. For applications with stringent throughput constraints, the allocation is often done manually by carefully assigning static memory locations to the logical buffers of the application. Today, designers are confronted with applications with thousands of buffers and architectures with hundreds of memories, rendering manual approaches impractical. In this paper we present an automatic approach for statically allocating logical buffers to physical memories, assuming a fixed task-to-processor mapping and respecting multiple throughput constraints.
In our approach, we model the application in a data-centric way, by explicitly defining buffers and associating computational tasks that access the buffers within well-specified time intervals. Besides, we use an architecture model that allows to perform an allocation that is aware of the topology of the multicore and the physical bandwidth constraints of the interconnect. We present a layered approach to describe and solve the buffer-allocation problem as well as related subproblems, using mixed-integer linear pro- gramming. We show that the buffer-allocation problem is NP-complete, and present a more scalable formulation as a semi-definite programming problem. We evaluate the proposed LP methods by allocating around 1000 buffers corresponding to processing one frame in the Long-Term Evolution (LTE) standard, onto a multicore with 80 processing elements. We introduce a solution approach that allowed to find an optimal allocation in around 2 hours, which is at least two orders of magnitude faster than a straightforward formulation.Bibtex
@Article{goens_jsa16,
Title={An Optimal Allocation of Memory Buffers for Complex Multicore Platforms},
Author={Goens, Andr\'{e}s and Castrillon, Jeronimo and Odendahl, Maximilian and Leupers, Rainer},
Journal={Journal of Systems Architecture},
volume={66-67},
pages={69--83},
doi={10.1016/j.sysarc.2016.05.002},
publisher={Elsevier},
Year={2016},
month=may,
abstract={In deeply embedded heterogeneous multicores the allocation of data to memories is crucial for application performance. For applications with stringent throughput constraints, the allocation is often done manually by carefully assigning static memory locations to the logical buffers of the application. Today, designers are confronted with applications with thousands of buffers and architectures with hundreds of memories, rendering manual approaches impractical. In this paper we present an automatic approach for statically allocating logical buffers to physical memories, assuming a fixed task-to-processor mapping and respecting multiple throughput constraints.
In our approach, we model the application in a data-centric way, by explicitly defining buffers and associating computational tasks that access the buffers within well-specified time intervals. Besides, we use an architecture model that allows to perform an allocation that is aware of the topology of the multicore and the physical bandwidth constraints of the interconnect. We present a layered approach to describe and solve the buffer-allocation problem as well as related subproblems, using mixed-integer linear pro- gramming. We show that the buffer-allocation problem is NP-complete, and present a more scalable formulation as a semi-definite programming problem. We evaluate the proposed LP methods by allocating around 1000 buffers corresponding to processing one frame in the Long-Term Evolution (LTE) standard, onto a multicore with 80 processing elements. We introduce a solution approach that allowed to find an optimal allocation in around 2 hours, which is at least two orders of magnitude faster than a straightforward formulation.}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Pham Nam Khanh, Akash Kumar, Khin Mi Mi Aung, "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES, Sankt Goar, Germany, May 23-25, 2016, pp. 127–134, May 2016. (Awarded with Best presentation award of SCOPES 2016) [doi] [Bibtex & Downloads]
Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms
×Reference
Pham Nam Khanh, Akash Kumar, Khin Mi Mi Aung, "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES, Sankt Goar, Germany, May 23-25, 2016, pp. 127–134, May 2016. (Awarded with Best presentation award of SCOPES 2016) [doi]
Bibtex
@inproceedings{DBLP:conf/scopes/KhanhKA16,
author={Khanh, Pham Nam and Kumar, Akash and Aung, Khin Mi Mi},
title={Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms},
booktitle={Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, {SCOPES}, Sankt Goar, Germany, May 23-25, 2016},
pages={127--134},
year={2016},
month={May},
crossref={DBLP:conf/scopes/2016},
url={http://doi.acm.org/10.1145/2906363.2906380},
doi={10.1145/2906363.2906380},
}Downloads
scopes_2016_camera_ready [PDF]
Related Paths
Permalink
- N. U. Hassan, M. Schlüter, G. P. Fettweis, "Fully parallel window decoder architecture for spatially-coupled LDPC codes", In Proceeding: 2016 IEEE International Conference on Communications (ICC), pp. 1-6, May 2016. [Bibtex & Downloads]
Fully parallel window decoder architecture for spatially-coupled LDPC codes
×Reference
N. U. Hassan, M. Schlüter, G. P. Fettweis, "Fully parallel window decoder architecture for spatially-coupled LDPC codes", In Proceeding: 2016 IEEE International Conference on Communications (ICC), pp. 1-6, May 2016.
Bibtex
@INPROCEEDINGS{HassanHAEC2016-1,
author={N. U. Hassan and M. Schlüter and G. P. Fettweis},
booktitle={2016 IEEE International Conference on Communications (ICC)},
title={Fully parallel window decoder architecture for spatially-coupled LDPC codes},
year={2016},
pages={1-6},
month={May},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Nils Asmussen, Marcus Völp, Benedikt Nöthen, Hermann Härtig, Gerhard Fettweis, "M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores" (to appear), Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, April 2016. [Bibtex & Downloads]
M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores
×Reference
Nils Asmussen, Marcus Völp, Benedikt Nöthen, Hermann Härtig, Gerhard Fettweis, "M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores" (to appear), Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, April 2016.
Bibtex
@inproceedings{asmussen2016,
author={Asmussen, Nils and V\"olp, Marcus and N\"othen, Benedikt and H\"artig, Hermann and Fettweis, Gerhard},
title={M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores},
booktitle={Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems},
series={ASPLOS},
year={2016},
month={April},
location={Atlanta, GA, USA},
publisher={ACM},
url={http://os.inf.tu-dresden.de/papers_ps/asmussen-m3-asplos16.pdf}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Jeronimo Castrillon, "Programming Heterogeneous Embedded Systems for IoT", In Workshop get-togethers toward a sustainable collaboration in IoT (invited talk), Apr 2016. ([link]) [Bibtex & Downloads]
Programming Heterogeneous Embedded Systems for IoT
×Reference
Jeronimo Castrillon, "Programming Heterogeneous Embedded Systems for IoT", In Workshop get-togethers toward a sustainable collaboration in IoT (invited talk), Apr 2016. ([link])
Bibtex
@Misc{castrillon2016tunis,
author={Castrillon, Jeronimo},
title={Programming Heterogeneous Embedded Systems for IoT},
howpublished={Workshop get-togethers toward a sustainable collaboration in IoT (invited talk)},
month=apr,
year={2016},
location={Tunis, Tunisia},
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/160418_castrillon_dataflow4IoT.pdf}
}Downloads
160418_castrillon_dataflow4IoT [PDF]
Related Paths
Permalink
- Sven Karol, Norman A. Rink, Bálint Gyapjas, Jeronimo Castrillon, "Fault Tolerance with Aspects: a Feasibility Study", Proceedings of the 15th International Conference on Modularity, ACM, pp. 66–69, New York, NY, USA, Mar 2016. [doi] [Bibtex & Downloads]
Fault Tolerance with Aspects: a Feasibility Study
×Reference
Sven Karol, Norman A. Rink, Bálint Gyapjas, Jeronimo Castrillon, "Fault Tolerance with Aspects: a Feasibility Study", Proceedings of the 15th International Conference on Modularity, ACM, pp. 66–69, New York, NY, USA, Mar 2016. [doi]
Bibtex
@inproceedings{karol2016faulttolerance,
author={Karol, Sven and Rink, Norman A. and Gyapjas, B\'{a}lint and Castrillon, Jeronimo},
title={Fault Tolerance with Aspects: a Feasibility Study},
booktitle={Proceedings of the 15th International Conference on Modularity},
series={MODULARITY 2016},
year={2016},
pages={66--69},
address={New York, NY, USA},
month={mar},
publisher={ACM},
doi={10.1145/2889443.2889453},
isbn={978-1-4503-3995-7/16/03},
location={M{\'a}laga, Spain},
}Downloads
1603_Karol_Modularity_preprint [PDF]
Related Paths
Permalink
- Christian Menard, "Mapping KPN-Based Applications to the NoC-Based Tomahawk Architectures", Master's thesis, TU Dresden, 3/2016. [Bibtex & Downloads]
Mapping KPN-Based Applications to the NoC-Based Tomahawk Architectures
×Reference
Christian Menard, "Mapping KPN-Based Applications to the NoC-Based Tomahawk Architectures", Master's thesis, TU Dresden, 3/2016.
Bibtex
@mastersthesis{Christian2016Mappin,
title={Mapping KPN-Based Applications to the NoC-Based Tomahawk Architectures},
author={Christian Menard},
year={2016},
month={3},
school={TU Dresden},
}Downloads
1603_Menard_DA [PDF]
Related Paths
Permalink
- Johannes Mey, Sven Karol, Uwe Aßmann, Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Using Semantics-Aware Composition and Weaving for Multi-Variant Progressive Parallelization" , In Procedia Computer Science, Elsevier, vol. 80, pp. 1554–1565, 2016. [doi] [Bibtex & Downloads]
Using Semantics-Aware Composition and Weaving for Multi-Variant Progressive Parallelization
×Reference
Johannes Mey, Sven Karol, Uwe Aßmann, Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Using Semantics-Aware Composition and Weaving for Multi-Variant Progressive Parallelization" , In Procedia Computer Science, Elsevier, vol. 80, pp. 1554–1565, 2016. [doi]
Bibtex
@article{karol16b,
Title={Using Semantics-Aware Composition and Weaving for Multi-Variant Progressive Parallelization},
Author={Johannes Mey and Sven Karol and Uwe Aßmann and Immo Huismann and Jörg Stiller and Jochen Fröhlich},
journal={Procedia Computer Science},
volume={80},
pages={1554--1565},
note={International Conference on Computational Science 2016, \{ICCS\} 2016, 6-8 June 2016, San Diego,California,\{USA\},
issn={1877-0509},
year={2016},
doi={10.1016/j.procs.2016.05.482},
Publisher ={Elsevier},
}
Downloads
No Downloads available for this publication
Related Paths
Permalink
- Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Fast static condensation for the Helmholtz equation in a
spectral-element discretization", Chapter in Parallel Processing and Applied Mathematics, Springer, pp. 371–380, 2016. [doi] [Bibtex & Downloads]
Fast static condensation for the Helmholtz equation in a spectral-element discretization
×Reference
Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Fast static condensation for the Helmholtz equation in a spectral-element discretization", Chapter in Parallel Processing and Applied Mathematics, Springer, pp. 371–380, 2016. [doi]
Bibtex
@InCollection{huismann_2016_condensation,
author= {Huismann, Immo and Stiller, J{\"o}rg and Fr{\"o}hlich, Jochen},
title= {Fast static condensation for the Helmholtz equation in a
spectral-element discretization},
booktitle= {Parallel Processing and Applied Mathematics},
publisher= {Springer},
year= {2016},
pages= {371--380},
doi= {10.1007/978-3-319-32152-3_35},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung, "Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures", In Microprocessors and Microsystems, 2016. [Bibtex & Downloads]
Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures
×Reference
Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung, "Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures", In Microprocessors and Microsystems, 2016.
Bibtex
@article{Khanh-Micpro-2016,
title = {Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures},
journal = {Microprocessors and Microsystems },
year = {2016},
author = {Pham Nam Khanh and Amit Kumar Singh and Akash Kumar and Khin Mi Mi Aung}
}Downloads
MICPRO-2016-Khanh [PDF]
Related Paths
Permalink
- Christel Baier, Sascha Klüppelholz, Hermann de Meer, Florian Niedermeier, Sascha Wunderlich, "Greener Bits: Formal Analysis of Demand Response", In Proceeding: Proc. of the 14th International Symposium on Automated Technology for Verification and Analysis (ATVA), Springer, vol. 9938, pp. 323–339, 2016. [doi] [Bibtex & Downloads]
Greener Bits: Formal Analysis of Demand Response
×Reference
Christel Baier, Sascha Klüppelholz, Hermann de Meer, Florian Niedermeier, Sascha Wunderlich, "Greener Bits: Formal Analysis of Demand Response", In Proceeding: Proc. of the 14th International Symposium on Automated Technology for Verification and Analysis (ATVA), Springer, vol. 9938, pp. 323–339, 2016. [doi]
Bibtex
@inproceedings{BKMNW16,
author = {Christel Baier and Sascha Kl{\"u}ppelholz and Hermann de Meer and Florian Niedermeier and Sascha Wunderlich},
title = {Greener Bits: Formal Analysis of Demand Response},
booktitle = {Proc. of the 14th International Symposium on Automated Technology for Verification and Analysis (ATVA)},
pages = {323--339},
year = {2016},
doi = {10.1007/978-3-319-46520-3_21},
series = {Lecture Notes in Computer Science},
volume = {9938},
publisher = {Springer},
ee = {http://dx.doi.org/10.1007/978-3-319-46520-3_21},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, "Cost-Utility Analysis in Probabilistic Models", In Proceeding: Proc. of the 10th International Symposium on Theoretical Aspects of Software Engineering (TASE), IEEE, pp. 1, 2016. [doi] [Bibtex & Downloads]
Cost-Utility Analysis in Probabilistic Models
×Reference
Christel Baier, "Cost-Utility Analysis in Probabilistic Models", In Proceeding: Proc. of the 10th International Symposium on Theoretical Aspects of Software Engineering (TASE), IEEE, pp. 1, 2016. [doi]
Bibtex
@inproceedings{B16-TASE,
author = {Christel Baier},
title = {Cost-Utility Analysis in Probabilistic Models},
booktitle = {Proc. of the 10th International Symposium on Theoretical Aspects of Software Engineering (TASE)},
pages = {1},
year = {2016},
doi = {http://dx.doi.org/10.1109/TASE.2016.10},
publisher = ,
note = {Abstract for invited talk}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Daniel Gburek, Christel Baier, Sascha Klüppelholz, "Composition of Stochastic Transition Systems Based on Spans and Couplings", In Proceeding: Proc. of the 43rd International Colloquium on Automata, Languages and Programming (ICALP), Schloss Dagstuhl - Leibniz-Zentrum für Informatik, vol. 55, pp. 102:1–102:15, 2016. [Bibtex & Downloads]
Composition of Stochastic Transition Systems Based on Spans and Couplings
×Reference
Daniel Gburek, Christel Baier, Sascha Klüppelholz, "Composition of Stochastic Transition Systems Based on Spans and Couplings", In Proceeding: Proc. of the 43rd International Colloquium on Automata, Languages and Programming (ICALP), Schloss Dagstuhl - Leibniz-Zentrum für Informatik, vol. 55, pp. 102:1–102:15, 2016.
Bibtex
@inproceedings{GBK16,
author = {Daniel Gburek and Christel Baier and Sascha Kl{\"u}ppelholz},
title = {Composition of Stochastic Transition Systems Based on Spans and Couplings},
booktitle = {Proc. of the 43rd International Colloquium on Automata, Languages and Programming (ICALP)},
year = {2016},
volume = {55},
pages = {102:1--102:15},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"u}r Informatik},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Stefan Kiefer, Joachim Klein, Sascha Klüppelholz, David Müller, James Worrell, "Markov Chains and Unambiguous Büchi Automata", In Proceeding: Proc. of the 28th International Conference on Computer Aided Verification (CAV) - Part I, Springer, vol. 9779, pp. 23–42, 2016. [Bibtex & Downloads]
Markov Chains and Unambiguous Büchi Automata
×Reference
Christel Baier, Stefan Kiefer, Joachim Klein, Sascha Klüppelholz, David Müller, James Worrell, "Markov Chains and Unambiguous Büchi Automata", In Proceeding: Proc. of the 28th International Conference on Computer Aided Verification (CAV) - Part I, Springer, vol. 9779, pp. 23–42, 2016.
Bibtex
@inproceedings{BKKKMW16,
author = {Christel Baier and Stefan Kiefer and Joachim Klein and Sascha Kl{\"u}ppelholz and David M{\"u}ller and James Worrell},
title = {Markov Chains and Unambiguous {B{\"u}chi} Automata},
booktitle = {Proc. of the 28th International Conference on Computer Aided Verification (CAV) - Part {I}},
year = {2016},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
volume = {9779},
pages = {23--42},
ee = {http://dx.doi.org/10.1007/978-3-319-41528-4_2},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Joachim Klein, Christel Baier, Philipp Chrszon, Marcus Daum, Clemens Dubslaff, Sascha Klüppelholz, Steffen Märcker, David Müller, "Advances in Symbolic Probabilistic
Model Checking with PRISM", In Proceeding: Proc. of the 22th International Conference on
Tools and Algorithms
for the Construction and Analysis of Systems (TACAS), Springer, vol. 9636, pp. 349–366, 2016. [Bibtex & Downloads]
Advances in Symbolic Probabilistic Model Checking with PRISM
×Reference
Joachim Klein, Christel Baier, Philipp Chrszon, Marcus Daum, Clemens Dubslaff, Sascha Klüppelholz, Steffen Märcker, David Müller, "Advances in Symbolic Probabilistic Model Checking with PRISM", In Proceeding: Proc. of the 22th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Springer, vol. 9636, pp. 349–366, 2016.
Bibtex
@inproceedings{KBCDDKMM16,
author = {Joachim Klein and Christel Baier and Philipp Chrszon and Marcus Daum and Clemens Dubslaff and Sascha Kl{\"u}ppelholz and Steffen M{\"a}rcker and David M{\"u}ller},
title = {Advances in Symbolic Probabilistic
Model Checking with {PRISM}},
booktitle = {Proc. of the 22th International Conference on
Tools and Algorithms
for the Construction and Analysis of Systems (TACAS)},
pages = {349--366},
year = {2016},
series = {Lecture Notes in Computer Science},
volume = {9636},
publisher = {Springer},
ee = {http://dx.doi.org/10.1007/978-3-662-49674-9_20},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Philipp Chrszon, Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "Family-Based Modeling and Analysis for
Probabilistic Systems - Featuring ProFeat", In Proceeding: Proc. of the 19th International Conference on
Fundamental Approaches to Software Engineering (FASE), Springer, vol. 9633, pp. 287–304, 2016. [Bibtex & Downloads]
Family-Based Modeling and Analysis for Probabilistic Systems - Featuring ProFeat
×Reference
Philipp Chrszon, Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "Family-Based Modeling and Analysis for Probabilistic Systems - Featuring ProFeat", In Proceeding: Proc. of the 19th International Conference on Fundamental Approaches to Software Engineering (FASE), Springer, vol. 9633, pp. 287–304, 2016.
Bibtex
@inproceedings{CDKB16,
author = {Philipp Chrszon, Clemens Dubslaff, Sascha Kl{\"u}ppelholz, Christel Baier},
title = {Family-Based Modeling and Analysis for
Probabilistic Systems - Featuring {ProFeat}},
booktitle = {Proc. of the 19th International Conference on
Fundamental Approaches to Software Engineering (FASE)},
pages = {287--304},
year = {2016},
ee = {http://dx.doi.org/10.1007/978-3-662-49665-7_17},
series = {Lecture Notes in Computer Science},
volume = {9633},
publisher = {Springer},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Philipp Chrszon, Clemens Dubslaff, Christel Baier, Joachim Klein, Sascha Klüppelholz, "Modeling Role-Based Systems with Exogenous Coordination", In Proceeding: Theory and Practice of Formal Methods - Essays Dedicated to Frank
de Boer on the Occasion of His 60th Birthday, Springer, vol. 9660, pp. 122–139, 2016. [Bibtex & Downloads]
Modeling Role-Based Systems with Exogenous Coordination
×Reference
Philipp Chrszon, Clemens Dubslaff, Christel Baier, Joachim Klein, Sascha Klüppelholz, "Modeling Role-Based Systems with Exogenous Coordination", In Proceeding: Theory and Practice of Formal Methods - Essays Dedicated to Frank de Boer on the Occasion of His 60th Birthday, Springer, vol. 9660, pp. 122–139, 2016.
Bibtex
@inproceedings{CDBKK16,
author = {Philipp Chrszon, Clemens Dubslaff, Christel Baier, Joachim Klein, Sascha Kl{\"u}ppelholz},
title = {Modeling Role-Based Systems with Exogenous Coordination},
booktitle = {Theory and Practice of Formal Methods - Essays Dedicated to Frank
de Boer on the Occasion of His 60th Birthday},
pages = {122--139},
ee = {http://dx.doi.org/10.1007/978-3-319-30734-3_10},
series = {Lecture Notes in Computer Science},
volume = {9660},
publisher = {Springer},
year = {2016},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Matthias Lieber, Kerstin Gößner, Wolfgang E. Nagel, "The Potential of Diffusive Load Balancing at Large Scale", Proceedings of the 23rd European MPI Users' Group Meeting, ACM, pp. 154–157, 2016. [doi] [Bibtex & Downloads]
The Potential of Diffusive Load Balancing at Large Scale
×Reference
Matthias Lieber, Kerstin Gößner, Wolfgang E. Nagel, "The Potential of Diffusive Load Balancing at Large Scale", Proceedings of the 23rd European MPI Users' Group Meeting, ACM, pp. 154–157, 2016. [doi]
Bibtex
@inproceedings{Lieber:2016:PDL:2966884.2966887,
author = {Lieber, Matthias and G\"{o}\ssner, Kerstin and Nagel, Wolfgang E.},
title = {The Potential of Diffusive Load Balancing at Large Scale},
booktitle = {Proceedings of the 23rd European MPI Users' Group Meeting},
series = {EuroMPI 2016},
year = {2016},
location = {Edinburgh, United Kingdom},
pages = {154--157},
url = {http://doi.acm.org/10.1145/2966884.2966887},
doi = {10.1145/2966884.2966887},
publisher = {ACM},
keywords = {Dynamic Load Balancing, HPC, Workload Diffusion}
}Downloads
2016-eurompi-diffusion [PDF]
Related Paths
Permalink
- Tomas Karnagel, "Heterogeneity-Aware Query Optimization", In Proceeding: VLDB 2016 PhD Workshop, 2016. [Bibtex & Downloads]
Heterogeneity-Aware Query Optimization
×Reference
Tomas Karnagel, "Heterogeneity-Aware Query Optimization", In Proceeding: VLDB 2016 PhD Workshop, 2016.
Bibtex
@inproceedings{karnagel2016heterogeneity,
title={Heterogeneity-Aware Query Optimization},
author={Karnagel, Tomas},
booktitle={VLDB 2016 PhD Workshop},
year={2016}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomas Karnagel, Dirk Habich, Wolfgang Lehner, "Limitations of Intra-operator Parallelism Using Heterogeneous Computing Resources", Springer International Publishing, pp. 291–305, Cham, 2016. [doi] [Bibtex & Downloads]
Limitations of Intra-operator Parallelism Using Heterogeneous Computing Resources
×Reference
Tomas Karnagel, Dirk Habich, Wolfgang Lehner, "Limitations of Intra-operator Parallelism Using Heterogeneous Computing Resources", Springer International Publishing, pp. 291–305, Cham, 2016. [doi]
Bibtex
@Inbook{Karnagel2016,
author="Karnagel, Tomas and Habich, Dirk and Lehner, Wolfgang",
editor="Pokorn{\'y}, Jaroslav and Ivanovi{\'{c}}, Mirjana and Thalheim, Bernhard and {\v{S}}aloun, Petr",
title="Limitations of Intra-operator Parallelism Using Heterogeneous Computing Resources",
bookTitle="Advances in Databases and Information Systems: 20th East European Conference, ADBIS 2016, Prague, Czech Republic, August 28-31, 2016, Proceedings",
year="2016",
publisher="Springer International Publishing",
address="Cham",
pages="291--305",
isbn="978-3-319-44039-2",
doi="10.1007/978-3-319-44039-2_20",
url="http://dx.doi.org/10.1007/978-3-319-44039-2_20"
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Jörg Stiller, "Robust multigrid for high-order discontinuous Galerkin methods: A fast Poisson solver suitable for high-aspect ratio Cartesian grids", In arXiv preprint arXiv:1603.02524, 2016. [Bibtex & Downloads]
Robust multigrid for high-order discontinuous Galerkin methods: A fast Poisson solver suitable for high-aspect ratio Cartesian grids
×Reference
Jörg Stiller, "Robust multigrid for high-order discontinuous Galerkin methods: A fast Poisson solver suitable for high-aspect ratio Cartesian grids", In arXiv preprint arXiv:1603.02524, 2016.
Bibtex
@article{stiller2016robust,
title={Robust multigrid for high-order discontinuous Galerkin methods: A fast Poisson solver suitable for high-aspect ratio Cartesian grids},
author={Stiller, J{\"o}rg},
journal={arXiv preprint arXiv:1603.02524},
year={2016}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Orchestration Path
Permalink
- Christel Baier, Stefan Kiefer, Joachim Klein, Sascha Klüppelholz, David Müller, James Worrell, "Markov Chains and Unambiguous B$\backslash$" uchi Automata", In arXiv preprint arXiv:1605.00950, 2016. [Bibtex & Downloads]
Markov Chains and Unambiguous B$\backslash$" uchi Automata
×Reference
Christel Baier, Stefan Kiefer, Joachim Klein, Sascha Klüppelholz, David Müller, James Worrell, "Markov Chains and Unambiguous B$\backslash$" uchi Automata", In arXiv preprint arXiv:1605.00950, 2016.
Bibtex
@article{baier2016markov,
title={Markov Chains and Unambiguous B$\backslash$" uchi Automata},
author={Baier, Christel and Kiefer, Stefan and Klein, Joachim and Kl{\"u}ppelholz, Sascha and M{\"u}ller, David and Worrell, James},
journal={arXiv preprint arXiv:1605.00950},
year={2016}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path, other
Permalink
- Sebastian Haas, Oliver Arnold, Stefan Scholze, Sebastian Höppner, Georg Ellguth, Andreas Dixius, Annett Ungethüm, Eric Mier, Benedikt Nöthen, Emil Matúš, others, "A database accelerator for energy-efficient query processing and optimization", In Proceeding: Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE, pp. 1–5, 2016. [Bibtex & Downloads]
A database accelerator for energy-efficient query processing and optimization
×Reference
Sebastian Haas, Oliver Arnold, Stefan Scholze, Sebastian Höppner, Georg Ellguth, Andreas Dixius, Annett Ungethüm, Eric Mier, Benedikt Nöthen, Emil Matúš, others, "A database accelerator for energy-efficient query processing and optimization", In Proceeding: Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE, pp. 1–5, 2016.
Bibtex
@inproceedings{haas2016database,
title={A database accelerator for energy-efficient query processing and optimization},
author={Haas, Sebastian and Arnold, Oliver and Scholze, Stefan and H{\"o}ppner, Sebastian and Ellguth, Georg and Dixius, Andreas and Ungeth{\"u}m, Annett and Mier, Eric and N{\"o}then, Benedikt and Mat{\'u}{\v{s}}, Emil and others},
booktitle={Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE},
pages={1--5},
year={2016},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Orchestration Path
Permalink
- Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Cascadic Multigrid in a Spectral-Element Context", In PAMM, Wiley Online Library, vol. 16, no. 1, pp. 841–842, 2016. [Bibtex & Downloads]
Cascadic Multigrid in a Spectral-Element Context
×Reference
Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Cascadic Multigrid in a Spectral-Element Context", In PAMM, Wiley Online Library, vol. 16, no. 1, pp. 841–842, 2016.
Bibtex
@article{huismann2016cascadic,
title={Cascadic Multigrid in a Spectral-Element Context},
author={Huismann, Immo and Stiller, J{\"o}rg and Fr{\"o}hlich, Jochen},
journal={PAMM},
volume={16},
number={1},
pages={841--842},
year={2016},
publisher={Wiley Online Library}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Orchestration Path
Permalink
- Joerg Stiller, "Robust Multigrid for Cartesian Interior Penalty DG Formulations of the Poisson Equation in 3D", In arXiv preprint arXiv:1612.04796, 2016. [Bibtex & Downloads]
Robust Multigrid for Cartesian Interior Penalty DG Formulations of the Poisson Equation in 3D
×Reference
Joerg Stiller, "Robust Multigrid for Cartesian Interior Penalty DG Formulations of the Poisson Equation in 3D", In arXiv preprint arXiv:1612.04796, 2016.
Bibtex
@article{stiller2016robust,
title={Robust Multigrid for Cartesian Interior Penalty DG Formulations of the Poisson Equation in 3D},
author={Stiller, Joerg},
journal={arXiv preprint arXiv:1612.04796},
year={2016}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, other
Permalink
- Jörg Stiller, "Nonuniformly weighted Schwarz smoothers for spectral element multigrid", In Journal of Scientific Computing, Springer, pp. 1–16, 2016. [Bibtex & Downloads]
Nonuniformly weighted Schwarz smoothers for spectral element multigrid
×Reference
Jörg Stiller, "Nonuniformly weighted Schwarz smoothers for spectral element multigrid", In Journal of Scientific Computing, Springer, pp. 1–16, 2016.
Bibtex
@article{stiller2016nonuniformly,
title={Nonuniformly weighted Schwarz smoothers for spectral element multigrid},
author={Stiller, J{\"o}rg},
journal={Journal of Scientific Computing},
pages={1--16},
year={2016},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Orchestration Path
Permalink
- Adam Lackorzynski, Carsten Weinhold, Hermann Härtig, "Combining Predictable Execution with Full-Featured Commodity Systems", In OSPERT 2016, pp. 31, 2016. [Bibtex & Downloads]
Combining Predictable Execution with Full-Featured Commodity Systems
×Reference
Adam Lackorzynski, Carsten Weinhold, Hermann Härtig, "Combining Predictable Execution with Full-Featured Commodity Systems", In OSPERT 2016, pp. 31, 2016.
Bibtex
@article{lackorzynski2016combining,
title={Combining Predictable Execution with Full-Featured Commodity Systems},
author={Lackorzynski, Adam and Weinhold, Carsten and H{\"a}rtig, Hermann},
journal={OSPERT 2016},
pages={31},
year={2016}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Romain Jacob, Marco Zimmerling, Pengcheng Huang, Jan Beutel, Lothar Thiele, "Towards Real-time Wireless Cyber-physical Systems", In Edited by Sebastian Altmeyer, pp. 7, 2016. [Bibtex & Downloads]
Towards Real-time Wireless Cyber-physical Systems
×Reference
Romain Jacob, Marco Zimmerling, Pengcheng Huang, Jan Beutel, Lothar Thiele, "Towards Real-time Wireless Cyber-physical Systems", In Edited by Sebastian Altmeyer, pp. 7, 2016.
Bibtex
@article{jacob2016towards,
title={Towards Real-time Wireless Cyber-physical Systems},
author={Jacob, Romain and Zimmerling, Marco and Huang, Pengcheng and Beutel, Jan and Thiele, Lothar},
journal={Edited by Sebastian Altmeyer},
pages={7},
year={2016}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Resilience Path
Permalink
- Carsten Weinhold, Adam Lackorzynski, Jan Bierbaum, Martin Küttler, Maksym Planeta, Hermann Härtig, Amnon Shiloh, Ely Levy, Tal Ben-Nun, Amnon Barak, others, "FFMK: a fast and fault-tolerant microkernel-based system for exascale computing", Chapter in Software for Exascale Computing-SPPEXA 2013-2015, Springer, pp. 405–426, 2016. [Bibtex & Downloads]
FFMK: a fast and fault-tolerant microkernel-based system for exascale computing
×Reference
Carsten Weinhold, Adam Lackorzynski, Jan Bierbaum, Martin Küttler, Maksym Planeta, Hermann Härtig, Amnon Shiloh, Ely Levy, Tal Ben-Nun, Amnon Barak, others, "FFMK: a fast and fault-tolerant microkernel-based system for exascale computing", Chapter in Software for Exascale Computing-SPPEXA 2013-2015, Springer, pp. 405–426, 2016.
Bibtex
@incollection{weinhold2016ffmk,
title={FFMK: a fast and fault-tolerant microkernel-based system for exascale computing},
author={Weinhold, Carsten and Lackorzynski, Adam and Bierbaum, Jan and K{\"u}ttler, Martin and Planeta, Maksym and H{\"a}rtig, Hermann and Shiloh, Amnon and Levy, Ely and Ben-Nun, Tal and Barak, Amnon and others},
booktitle={Software for Exascale Computing-SPPEXA 2013-2015},
pages={405--426},
year={2016},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, others, "An MPSoC for energy-efficient database query processing", In Proceeding: Design Automation Conference (DAC), 2016 53nd ACM/EDAC/IEEE, pp. 1–6, 2016. [Bibtex & Downloads]
An MPSoC for energy-efficient database query processing
×Reference
Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, others, "An MPSoC for energy-efficient database query processing", In Proceeding: Design Automation Conference (DAC), 2016 53nd ACM/EDAC/IEEE, pp. 1–6, 2016.
Bibtex
@inproceedings{haas2016mpsoc,
title={An MPSoC for energy-efficient database query processing},
author={Haas, Sebastian and Arnold, Oliver and N{\"o}then, Benedikt and Scholze, Stefan and Ellguth, Georg and Dixius, Andreas and H{\"o}ppner, Sebastian and Schiefer, Stefan and Hartmann, Stephan and Henker, Stephan and others},
booktitle={Design Automation Conference (DAC), 2016 53nd ACM/EDAC/IEEE},
pages={1--6},
year={2016},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Resilience Path
Permalink
- Jens Bartelt, Dan Zhang, Gerhard Fettweis, "Joint Uplink Radio Access and Fronthaul Reception Using MMSE Estimation", In IEEE Transactions on Communications, IEEE, 2016. [Bibtex & Downloads]
Joint Uplink Radio Access and Fronthaul Reception Using MMSE Estimation
×Reference
Jens Bartelt, Dan Zhang, Gerhard Fettweis, "Joint Uplink Radio Access and Fronthaul Reception Using MMSE Estimation", In IEEE Transactions on Communications, IEEE, 2016.
Bibtex
@article{bartelt2016joint,
title={Joint Uplink Radio Access and Fronthaul Reception Using MMSE Estimation},
author={Bartelt, Jens and Zhang, Dan and Fettweis, Gerhard},
journal={IEEE Transactions on Communications},
year={2016},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Adam Lackorzynski, Carsten Weinhold, Hermann Härtig, "Decoupled: Low-Effort Noise-Free Execution on Commodity Systems", Proceedings of the 6th International Workshop on Runtime and Operating Systems for Supercomputers, pp. 2, 2016. [Bibtex & Downloads]
Decoupled: Low-Effort Noise-Free Execution on Commodity Systems
×Reference
Adam Lackorzynski, Carsten Weinhold, Hermann Härtig, "Decoupled: Low-Effort Noise-Free Execution on Commodity Systems", Proceedings of the 6th International Workshop on Runtime and Operating Systems for Supercomputers, pp. 2, 2016.
Bibtex
@inproceedings{lackorzynski2016decoupled,
title={Decoupled: Low-Effort Noise-Free Execution on Commodity Systems},
author={Lackorzynski, Adam and Weinhold, Carsten and H{\"a}rtig, Hermann},
booktitle={Proceedings of the 6th International Workshop on Runtime and Operating Systems for Supercomputers},
pages={2},
year={2016},
organization={ACM}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
2015
- Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck, "RAW 2014: Random Number Generators on FPGAs", In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi] [Bibtex & Downloads]
RAW 2014: Random Number Generators on FPGAs
×Reference
Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck, "RAW 2014: Random Number Generators on FPGAs", In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi]
Bibtex
@article{Raitza:2015:RRN:2854101.2807699,
author={Raitza, Michael and Vogt, Markus and Hochberger, Christian and Pionteck, Thilo},
title={RAW 2014: Random Number Generators on FPGAs},
journal={ACM Trans. Reconfigurable Technol. Syst.},
issue_date={January 2016},
volume={9},
number={2},
month=dec,
year={2015},
issn={1936-7406},
pages={15:1--15:21},
articleno={15},
numpages={21},
url={http://doi.acm.org/10.1145/2807699},
doi={10.1145/2807699},
acmid={2807699},
publisher={ACM},
address={New York, NY, USA},
keywords={Entropy source, FPGA, X-radiation, active attack on random number generator, cryptography, magnetic field, power supply, technology invariance, temperature, true random number generator},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Christoff Bürger, Johannes Mey, René Schöne, Sven Karol, Daniel Langner, "Using Reference Attribute Grammar-Controlled Rewriting for Energy Auto-Tuning", Proceedings of the 10th International Workshop on Models@run.time (MRT), Nov 2015. ([link]) [Bibtex & Downloads]
Using Reference Attribute Grammar-Controlled Rewriting for Energy Auto-Tuning
×Reference
Christoff Bürger, Johannes Mey, René Schöne, Sven Karol, Daniel Langner, "Using Reference Attribute Grammar-Controlled Rewriting for Energy Auto-Tuning", Proceedings of the 10th International Workshop on Models@run.time (MRT), Nov 2015. ([link])
Bibtex
@InProceedings{karol15c,
Title={Using Reference Attribute Grammar-Controlled Rewriting for Energy Auto-Tuning},
Author={Christoff Bürger and Johannes Mey and René Schöne and Sven Karol and Daniel Langner},
Booktitle={Proceedings of the 10th International Workshop on Models@run.time (MRT)},
series={MRT'15},
Year={2015},
Month=nov,
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Andrés Goens, Jeronimo Castrillon, "Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs", In Proceeding: System Level Design from HW/SW to Memory for Embedded Systems. IESS 2015. IFIP Advances in Information and Communication Technology, vol 523 (Götz, Marcelo and Schirner, Gunar and Wehrmeister, Marco Aurélio and Al Faruque, Mohammad Abdullah and Rettberg, Achim), Springer International Publishing, pp. 116–127, Foz do Iguaçu, Brazil, Nov 2015. [doi] [Bibtex & Downloads]
Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs
×Reference
Andrés Goens, Jeronimo Castrillon, "Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs", In Proceeding: System Level Design from HW/SW to Memory for Embedded Systems. IESS 2015. IFIP Advances in Information and Communication Technology, vol 523 (Götz, Marcelo and Schirner, Gunar and Wehrmeister, Marco Aurélio and Al Faruque, Mohammad Abdullah and Rettberg, Achim), Springer International Publishing, pp. 116–127, Foz do Iguaçu, Brazil, Nov 2015. [doi]
Abstract
Current approaches for mapping Kahn Process Networks (KPN) and Dynamic Data Flow (DDF) applications rely on assumptions on the program behavior specific to an execution. Thus, a near-optimal mapping, computed for a given input data set, may become sub-optimal at run-time. This happens when a different data set induces a significantly different behavior. We address this problem by leveraging inherent mathematical structures of the dataflow models and the hardware architectures. On the side of the dataflow models, we rely on the monoid structure of histories and traces. This structure help us formalize the behavior of multiple executions of a given dynamic application. By defining metrics we have a formal framework for comparing the executions. On the side of the hardware, we take advantage of symmetries in the architecture to reduce the search space for the mapping problem. We evaluate our implementation on execution variations of a randomly-generated KPN application and on a low-variation JPEG encoder benchmark. Using the described methods we show that trace differences are not sufficient for characterizing performance losses. Additionally, using platform symmetries we manage to reduce the design space in the experiments by two orders of magnitude.
Bibtex
@InProceedings{goens_iess15,
author = {Goens, Andr\'{e}s and Castrillon, Jeronimo},
title = {Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs},
booktitle = {System Level Design from HW/SW to Memory for Embedded Systems. IESS 2015. IFIP Advances in Information and Communication Technology, vol 523},
year = {2015},
editor = {G{\"o}tz, Marcelo and Schirner, Gunar and Wehrmeister, Marco Aur{\'e}lio and Al Faruque, Mohammad Abdullah and Rettberg, Achim},
pages = {116--127},
address = {Foz do Igua{\c{c}}u, Brazil},
month = nov,
publisher = {Springer International Publishing},
doi = {10.1007/978-3-319-90023-0_10},
url = {https://link.springer.com/chapter/10.1007%2F978-3-319-90023-0_10},
isbn={978-3-319-90023-0},
abstract = {Current approaches for mapping Kahn Process Networks (KPN) and Dynamic Data Flow (DDF) applications rely on assumptions on the program behavior specific to an execution. Thus, a near-optimal mapping, computed for a given input data set, may become sub-optimal at run-time. This happens when a different data set induces a significantly different behavior. We address this problem by leveraging inherent mathematical structures of the dataflow models and the hardware architectures. On the side of the dataflow models, we rely on the monoid structure of histories and traces. This structure help us formalize the behavior of multiple executions of a given dynamic application. By defining metrics we have a formal framework for comparing the executions. On the side of the hardware, we take advantage of symmetries in the architecture to reduce the search space for the mapping problem. We evaluate our implementation on execution variations of a randomly-generated KPN application and on a low-variation JPEG encoder benchmark. Using the described methods we show that trace differences are not sufficient for characterizing performance losses. Additionally, using platform symmetries we manage to reduce the design space in the experiments by two orders of magnitude.},
}Downloads
1511_Goens_IESS [PDF]
Related Paths
Permalink
- Benjamin Schiller, Jeronimo Castrillon, Thorsten Strufe, "Efficient data structures for dynamic graph analysis", Proceedings of the 11th International Conference on Signal-Image Technology & Internet-Based Systems (SITIS) (Lisa O'Conner), IEEE Computer Society, pp. 497–504, Bangkok, Thailand, Nov 2015. [doi] [Bibtex & Downloads]
Efficient data structures for dynamic graph analysis
×Reference
Benjamin Schiller, Jeronimo Castrillon, Thorsten Strufe, "Efficient data structures for dynamic graph analysis", Proceedings of the 11th International Conference on Signal-Image Technology & Internet-Based Systems (SITIS) (Lisa O'Conner), IEEE Computer Society, pp. 497–504, Bangkok, Thailand, Nov 2015. [doi]
Bibtex
@InProceedings{schiller_sitis15,
Title={Efficient data structures for dynamic graph analysis},
Author={Schiller, Benjamin and Castrillon, Jeronimo and Strufe, Thorsten},
Booktitle={Proceedings of the 11th International Conference on Signal-Image Technology \& Internet-Based Systems (SITIS)},
Year={2015},
Address={Bangkok, Thailand},
Editor={Lisa O'Conner},
Month=nov,
Publisher={IEEE Computer Society},
Series={SITIS 2015},
pages={497--504},
doi={10.1109/SITIS.2015.94}
}Downloads
1511_Schiller_SITIS [PDF]
Related Paths
Orchestration Path, Resilience Path, HAEC
Permalink
- Norman A. Rink, Jeronimo Castrillon, "Improving Code Generation for Software-based Error Detection", Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with ESWEEK 2015, pp. 16–30, Amsterdam, The Netherlands, Oct 2015. ([link]) [Bibtex & Downloads]
Improving Code Generation for Software-based Error Detection
×Reference
Norman A. Rink, Jeronimo Castrillon, "Improving Code Generation for Software-based Error Detection", Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with ESWEEK 2015, pp. 16–30, Amsterdam, The Netherlands, Oct 2015. ([link])
Bibtex
@InProceedings{rink_ress15,
Title={Improving Code Generation for Software-based Error Detection},
Author={Rink, Norman A. and Castrillon, Jeronimo},
Booktitle={Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with ESWEEK 2015},
Year={2015},
Series={REES 2015},
Address={Amsterdam, The Netherlands},
Month=oct,
Pages={16--30},
}Downloads
1510_Rink_REES [PDF]
Related Paths
Orchestration Path, Resilience Path
Permalink
- Jeronimo Castrillon, "Analysis and software synthesis of KPN applications", In Design of Robotics and Embedded systems, Analysis, and Modeling Seminar (DREAMS) (invited talk), Oct 2015. ([link]) [Bibtex & Downloads]
Analysis and software synthesis of KPN applications
×Reference
Jeronimo Castrillon, "Analysis and software synthesis of KPN applications", In Design of Robotics and Embedded systems, Analysis, and Modeling Seminar (DREAMS) (invited talk), Oct 2015. ([link])
Abstract
Programming models based on dataflow or process
networks are a good match for streaming
applications, common in the signal processing,
multimedia and automotive domains. In such models,
parallelism is expressed explicitly which makes
them well-suited for programming parallel
machines. Since today's applications are no
longer static, expressive programming models are
needed, such as those based on Kahn Process
Networks (KPNs). In these models, tasks cannot be
handled as black boxes, but have to be analyzed,
profiled and traced to characterize their
behavior. This is especially important in the case
of heterogenous platforms with many processors of
multiple different types. This presentation
describes a tool flow to handle KPN applications
and gives insights into mapping algorithms for
heterogeneous platforms.Bibtex
@Misc{castrillon15_dreams,
Title={Analysis and software synthesis of KPN applications},
Author={Jeronimo Castrillon},
HowPublished={Design of Robotics and Embedded systems, Analysis, and Modeling Seminar (DREAMS) (invited talk)},
Month=oct,
Year={2015},
Day={22},
Location={Berkeley, CA, USA},
Abstract={Programming models based on dataflow or process
networks are a good match for streaming
applications, common in the signal processing,
multimedia and automotive domains. In such models,
parallelism is expressed explicitly which makes
them well-suited for programming parallel
machines. Since today's applications are no
longer static, expressive programming models are
needed, such as those based on Kahn Process
Networks (KPNs). In these models, tasks cannot be
handled as black boxes, but have to be analyzed,
profiled and traced to characterize their
behavior. This is especially important in the case
of heterogenous platforms with many processors of
multiple different types. This presentation
describes a tool flow to handle KPN applications
and gives insights into mapping algorithms for
heterogeneous platforms.},
url={https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/151022_castrillon_dreams.pdf},
}Downloads
151022_castrillon_dreams [PDF]
Related Paths
Orchestration Path, Resilience Path
Permalink
- Jeronimo Castrillon, "Dataflow programming for heterogeneous computing systems", In Tutorial Algorithmic Specification, Tools and Algorithms for Programming Heterogeneous Platforms. Co-located with the 24th International Conference on Parallel Architectures and Compilation Techniques (PACT'15), Oct 2015. ([link]) [Bibtex & Downloads]
Dataflow programming for heterogeneous computing systems
×Reference
Jeronimo Castrillon, "Dataflow programming for heterogeneous computing systems", In Tutorial Algorithmic Specification, Tools and Algorithms for Programming Heterogeneous Platforms. Co-located with the 24th International Conference on Parallel Architectures and Compilation Techniques (PACT'15), Oct 2015. ([link])
Abstract
This tutorial talk starts by introducing new types of heterogeneous systems and their challenges for hardware/software programming stacks. These systems are currently being investigated in the context of the German cluster of excellence Cfaed – ''Center for Advancing Electronics Dresden''. We will then look at dataflow modeling concepts, with emphasis on the dynamic models that are needed to express today's changing workloads. Finally, the talk will introduce methods and algorithms for mapping sets of applications modeled in this way to heterogeneous systems.
Bibtex
@Misc{castrillon15_pacttut,
Title={Dataflow programming for heterogeneous computing systems},
Author={Jeronimo Castrillon},
HowPublished={Tutorial Algorithmic Specification, Tools and Algorithms for Programming Heterogeneous Platforms. Co-located with the 24th International Conference on Parallel Architectures and Compilation Techniques (PACT'15)},
Month=oct,
Year={2015},
Abstract={This tutorial talk starts by introducing new types of heterogeneous systems and their challenges for hardware/software programming stacks. These systems are currently being investigated in the context of the German cluster of excellence Cfaed – ''Center for Advancing Electronics Dresden''. We will then look at dataflow modeling concepts, with emphasis on the dynamic models that are needed to express today's changing workloads. Finally, the talk will introduce methods and algorithms for mapping sets of applications modeled in this way to heterogeneous systems.},
Day={18},
}Downloads
151018_castrillon_dataflow_pacttut [PDF]
Related Paths
Permalink
- Markus Vogt, Gerald Hempel, Jeronimo Castrillon, Christian Hochberger, "GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs", Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP), Sep 2015. ([link]) [Bibtex & Downloads]
GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs
×Reference
Markus Vogt, Gerald Hempel, Jeronimo Castrillon, Christian Hochberger, "GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs", Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP), Sep 2015. ([link])
Abstract
In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular. Such hybrid architectures allow extending embedded software with application specific hardware accelerators to improve performance and/or energy efficiency. Aiding system designers and programmers at handling the complexity of the required process of hardware/software (HW/SW) partitioning is an important issue. Current methods are often restricted, either to bare-metal systems, to subsets of mainstream programming languages, or require special coding guidelines, e.g., via annotations. These restrictions still represent a high entry barrier for the wider community of programmers that new hybrid architectures are intended for. In this paper we revisit HW/SW partitioning and present a seamless programming flow for unrestricted, legacy C code. It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly. The proposed workflow was evaluated on the Xilinx Zynq platform using unmodified code from an embedded benchmark suite.
Bibtex
@InProceedings{vogt15,
Title={GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs},
Author={Vogt , Markus and Hempel, Gerald and Castrillon, Jeronimo and Hochberger, Christian},
Booktitle={Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP)},
Year={2015},
Month=sep,
Series={FSP 2015},
archivePrefix={arXiv},
arxivId={1509.00025},
eprint={1509.00025},
abstract={In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular. Such hybrid architectures allow extending embedded software with application specific hardware accelerators to improve performance and/or energy efficiency. Aiding system designers and programmers at handling the complexity of the required process of hardware/software (HW/SW) partitioning is an important issue. Current methods are often restricted, either to bare-metal systems, to subsets of mainstream programming languages, or require special coding guidelines, e.g., via annotations. These restrictions still represent a high entry barrier for the wider community of programmers that new hybrid architectures are intended for. In this paper we revisit HW/SW partitioning and present a seamless programming flow for unrestricted, legacy C code. It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly. The proposed workflow was evaluated on the Xilinx Zynq platform using unmodified code from an embedded benchmark suite.},
}Downloads
1509_Vogt_FSP [PDF]
Related Paths
Permalink
- Jeronimo Castrillon, "Orchestration: Turning material breakthroughs into application performance", In Dresden Microelectronics Academy, (invited talk), Sep 2015. [Bibtex & Downloads]
Orchestration: Turning material breakthroughs into application performance
×Reference
Jeronimo Castrillon, "Orchestration: Turning material breakthroughs into application performance", In Dresden Microelectronics Academy, (invited talk), Sep 2015.
Bibtex
@Misc{castrillon2015dma,
Title={Orchestration: Turning material breakthroughs into application performance},
Author={Castrillon, Jeronimo},
HowPublished={Dresden Microelectronics Academy, (invited talk)},
Month=sep,
Year={2015},
Location={Dresden, Germany},
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/150918_castrillon_dma.pdf}
}Downloads
150918_castrillon_dma [PDF]
Related Paths
Permalink
- Norman A. Rink, Dmitrii Kuvaiskii, Jeronimo Castrillon, Christof Fetzer, "Compiling for Resilience: the Performance Gap", Chapter in Parallel Computing: On the Road to Exascale (ParCo 2015). Extended from Proceedings of the Mini-Symposium on Energy and Resilience in Parallel Programming (ERPP 2015) (Gerhard R. Joubert and Hugh Leather and Mark Parsons and Frans Peters and Mark Sawyer), IOS Press, vol. 27, pp. 721–730, Edinburgh, Scotland, Sep 2015. [doi] [Bibtex & Downloads]
Compiling for Resilience: the Performance Gap
×Reference
Norman A. Rink, Dmitrii Kuvaiskii, Jeronimo Castrillon, Christof Fetzer, "Compiling for Resilience: the Performance Gap", Chapter in Parallel Computing: On the Road to Exascale (ParCo 2015). Extended from Proceedings of the Mini-Symposium on Energy and Resilience in Parallel Programming (ERPP 2015) (Gerhard R. Joubert and Hugh Leather and Mark Parsons and Frans Peters and Mark Sawyer), IOS Press, vol. 27, pp. 721–730, Edinburgh, Scotland, Sep 2015. [doi]
Abstract
In order to perform reliable computations on unreliable hardware, software-based protection mechanisms have been proposed. In this paper we present a compiler infrastructure for software-based code hardening based on encoding. We analyze the trade-off between performance and fault coverage. We look at different code generation strategies that improve the performance of hardened programs by up to 2x while incurring little fault coverage degradation.
Bibtex
@InCollection{rink_erpp2015,
author={Rink, Norman A. and Kuvaiskii, Dmitrii and Castrillon, Jeronimo and Fetzer, Christof},
title={Compiling for Resilience: the Performance Gap},
booktitle={Parallel Computing: On the Road to Exascale (ParCo 2015). Extended from Proceedings of the Mini-Symposium on Energy and Resilience in Parallel Programming (ERPP 2015)},
publisher={IOS Press},
year={2015},
editor={Gerhard R. Joubert and Hugh Leather and Mark Parsons and Frans Peters and Mark Sawyer},
volume={27},
series={ParCo 2015},
pages={721--730},
address={Edinburgh, Scotland},
month=sep,
abstract={In order to perform reliable computations on unreliable hardware, software-based protection mechanisms have been proposed. In this paper we present a compiler infrastructure for software-based code hardening based on encoding. We analyze the trade-off between performance and fault coverage. We look at different code generation strategies that improve the performance of hardened programs by up to 2x while incurring little fault coverage degradation.},
doi={10.3233/978-1-61499-621-7-721},
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Resilience Path
Permalink
- Gerald Hempel, Markus Vogt, Jeronimo Castrillon, Christian Hochberger, "Software-Backed Caching and Virtual Addressing for Generated Accelerators in SoC FPGAs", Proceedings of 41st EUROMICRO Conference on Software Engineering and Advanced Applications - Work in Progress Session (Grosspietsch, Erwin and Klöckner, Konrad), SEA-Publications: SEA-SR-44, Funchal, Madeira (Portugal), August 2015. [Bibtex & Downloads]
Software-Backed Caching and Virtual Addressing for Generated Accelerators in SoC FPGAs
×Reference
Gerald Hempel, Markus Vogt, Jeronimo Castrillon, Christian Hochberger, "Software-Backed Caching and Virtual Addressing for Generated Accelerators in SoC FPGAs", Proceedings of 41st EUROMICRO Conference on Software Engineering and Advanced Applications - Work in Progress Session (Grosspietsch, Erwin and Klöckner, Konrad), SEA-Publications: SEA-SR-44, Funchal, Madeira (Portugal), August 2015.
Bibtex
@InProceedings{hempeldsd15,
Title={Software-Backed Caching and Virtual Addressing for Generated Accelerators in SoC FPGAs},
Author={Hempel, Gerald and Vogt, Markus and Castrillon, Jeronimo and Hochberger, Christian},
Booktitle={Proceedings of 41st EUROMICRO Conference on Software Engineering and Advanced Applications - Work in Progress Session},
Year={2015},
Address={Funchal, Madeira (Portugal)},
Editor={Grosspietsch, Erwin and Kl{\"o}ckner, Konrad},
Month={August},
Publisher={SEA-Publications: SEA-SR-44},
Series={DSD/SEAA 2015},
ISBN={978-3-902457-44-8}
}Downloads
1508_Hempel_DSD [PDF]
Related Paths
Permalink
- Sven Karol, Pietro Incardona, Yaser Afshar, Ivo Sbalzarini, Jeronimo Castrillon, "Towards a Next-Generation Parallel Particle-Mesh Language", Proceedings of the 3rd Workshop on Domain-Specific Language Design and Implementation (DSLDI), pp. 15–18, Jul 2015. ([link]) [Bibtex & Downloads]
Towards a Next-Generation Parallel Particle-Mesh Language
×Reference
Sven Karol, Pietro Incardona, Yaser Afshar, Ivo Sbalzarini, Jeronimo Castrillon, "Towards a Next-Generation Parallel Particle-Mesh Language", Proceedings of the 3rd Workshop on Domain-Specific Language Design and Implementation (DSLDI), pp. 15–18, Jul 2015. ([link])
Bibtex
@InProceedings{karol15,
Title={Towards a Next-Generation Parallel Particle-Mesh Language},
Author={Karol, Sven and Incardona, Pietro and Afshar, Yaser and Sbalzarini, Ivo and Castrillon, Jeronimo},
Booktitle={Proceedings of the 3rd Workshop on Domain-Specific Language Design and Implementation (DSLDI)},
series={DSLDI'15},
Year={2015},
Month=jul,
pages={15--18},
}Downloads
1507_Karol_PPML [PDF]
Related Paths
Permalink
- Nils Asmussen, Benedikt Nöthen, Marcus Völp, Oliver Arnold, Hermann Härtig, Gerhard Fettweis, "Uniform Control Over Heterogeneous Cores Through NoC-Level Isolation", In Proceeding: Design Automation Conference (DAC), Work in Progress Session, San Francisco, June 2015. [Bibtex & Downloads]
Uniform Control Over Heterogeneous Cores Through NoC-Level Isolation
×Reference
Nils Asmussen, Benedikt Nöthen, Marcus Völp, Oliver Arnold, Hermann Härtig, Gerhard Fettweis, "Uniform Control Over Heterogeneous Cores Through NoC-Level Isolation", In Proceeding: Design Automation Conference (DAC), Work in Progress Session, San Francisco, June 2015.
Bibtex
@inproceedings{asmussen2015uniform,
author={Nils Asmussen and Benedikt Nöthen and Marcus Völp and Oliver Arnold and Hermann Härtig and Gerhard Fettweis},
title={Uniform Control Over Heterogeneous Cores Through NoC-Level Isolation},
year={2015},
month={June},
booktitle={Design Automation Conference (DAC), Work in Progress Session, San Francisco},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Jeronimo Castrillon, "Portable Libraries and Programming Environments", In HiPEAC Computing Systems Week, (invited talk), May 2015. [Bibtex & Downloads]
Portable Libraries and Programming Environments
×Reference
Jeronimo Castrillon, "Portable Libraries and Programming Environments", In HiPEAC Computing Systems Week, (invited talk), May 2015.
Bibtex
@Misc{castrillon2015csw,
Title={Portable Libraries and Programming Environments},
Author={Castrillon, Jeronimo},
HowPublished={HiPEAC Computing Systems Week, (invited talk)},
Year={2015},
Month=may,
Location={Oslo, Noway},
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/150505_castrillon_csw.pdf}
}Downloads
150505_castrillon_csw [PDF]
Related Paths
Permalink
- Sven Karol, "Well-Formed and Scalable Invasive Software Composition", PhD thesis, TU Dresden, May 2015. ([pdf] [tool]) [Bibtex & Downloads]
Well-Formed and Scalable Invasive Software Composition
×Reference
Sven Karol, "Well-Formed and Scalable Invasive Software Composition", PhD thesis, TU Dresden, May 2015. ([pdf] [tool])
Bibtex
@phdthesis{karol2015well,
title={Well-Formed and Scalable Invasive Software Composition},
author={Sven Karol},
year={2015},
month={may},
school={TU Dresden},
}Downloads
skat_slides_no_animations [PDF]
Related Paths
Permalink
- A. Ungethum, D. Habich, T. Karnagel, W. Lehner, N. Asmussen, M. Volp, B. Nothen, G. Fettweis, "Query processing on low-energy many-core processors", In Proceeding: Data Engineering Workshops (ICDEW), 2015 31st IEEE International Conference on, pp. 155-160, April 2015. [doi] [Bibtex & Downloads]
Query processing on low-energy many-core processors
×Reference
A. Ungethum, D. Habich, T. Karnagel, W. Lehner, N. Asmussen, M. Volp, B. Nothen, G. Fettweis, "Query processing on low-energy many-core processors", In Proceeding: Data Engineering Workshops (ICDEW), 2015 31st IEEE International Conference on, pp. 155-160, April 2015. [doi]
Bibtex
@INPROCEEDINGS{7129569,
author={Ungethum, A. and Habich, D. and Karnagel, T. and Lehner, W. and Asmussen, N. and Volp, M. and Nothen, B. and Fettweis, G.},
booktitle={Data Engineering Workshops (ICDEW), 2015 31st IEEE International Conference on},
title={Query processing on low-energy many-core processors},
year={2015},
pages={155-160},
keywords={database management systems;hardware-software codesign;instruction sets;low-power electronics;multiprocessing systems;power aware computing;query processing;database systems;database-specific instruction set extensions;energy efficiency;energy requirement;hardware/software co-design approach;heterogeneous cores;low-energy many-core processors;low-energy processor design;query processing;single board chips;Arrays;Data transfer;Hardware;Program processors;Query processing},
doi={10.1109/ICDEW.2015.7129569},
month={April},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Jeronimo Castrillon, Lothar Thiele, Lars Schorr, Weihua Sheng, Ben Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers, "Multi/Many-core Programming: Where Are We Standing?", Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium, pp. 1708–1717, San Jose, CA, USA, Mar 2015. ([link]) [Bibtex & Downloads]
Multi/Many-core Programming: Where Are We Standing?
×Reference
Jeronimo Castrillon, Lothar Thiele, Lars Schorr, Weihua Sheng, Ben Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers, "Multi/Many-core Programming: Where Are We Standing?", Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium, pp. 1708–1717, San Jose, CA, USA, Mar 2015. ([link])
Bibtex
@inproceedings{Castrillon:2015,
author={Castrillon, Jeronimo and Thiele, Lothar and Schorr, Lars and Sheng, Weihua and Juurlink, Ben and Alvarez-Mesa, Mauricio and Pohl, Angela and Jessenberger, Ralph and Reyes, Victor and Leupers, Rainer},
title={Multi/Many-core Programming: Where Are We Standing?},
booktitle={Proceedings of the 2015 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
series={DATE '15},
year={2015},
Month=mar,
location={Grenoble, France},
pages={1708--1717},
numpages={10},
acmid={2757208},
publisher={EDA Consortium},
address={San Jose, CA, USA},
Bdsk-url-1={http://dl.acm.org/citation.cfm?id=2757012.2757208},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Nils Asmussen, Marcus Völp, "Taming Heterogeneous Accelerators: Operating-Systems for Cores with no OS Support", In Proceeding: 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Wild and Crazy Ideas Session, March 2015. [Bibtex & Downloads]
Taming Heterogeneous Accelerators: Operating-Systems for Cores with no OS Support
×Reference
Nils Asmussen, Marcus Völp, "Taming Heterogeneous Accelerators: Operating-Systems for Cores with no OS Support", In Proceeding: 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Wild and Crazy Ideas Session, March 2015.
Bibtex
@inproceedings{asmussen2015taming,
author={Nils Asmussen and Marcus Völp},
title={Taming Heterogeneous Accelerators: Operating-Systems for Cores with no OS Support},
year={2015},
month={March},
booktitle={20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Wild and Crazy Ideas Session},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Amnon Barak, Zvi Drezner, Ely Levy, Matthias Lieber, Amnon Shiloh, "Resilient gossip algorithms for collecting online management information in exascale clusters", In Concurrency and Computation: Practice and Experience, Wiley Online Library, vol. 27, no. 17, pp. 4797–4818, Jan 2015. [doi] [Bibtex & Downloads]
Resilient gossip algorithms for collecting online management information in exascale clusters
×Reference
Amnon Barak, Zvi Drezner, Ely Levy, Matthias Lieber, Amnon Shiloh, "Resilient gossip algorithms for collecting online management information in exascale clusters", In Concurrency and Computation: Practice and Experience, Wiley Online Library, vol. 27, no. 17, pp. 4797–4818, Jan 2015. [doi]
Bibtex
@article{barak2015resilient,
author={Barak, Amnon and Drezner, Zvi and Levy, Ely and Lieber, Matthias and Shiloh, Amnon},
doi={10.1002/cpe.3465},
journal={Concurrency and Computation: Practice and Experience},
month={jan},
number={17},
pages={4797–4818},
publisher={Wiley Online Library},
title={Resilient gossip algorithms for collecting online management information in exascale clusters},
url={https://doi.org/10.1002%2Fcpe.3465},
volume={27},
year={2015},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Jeronimo Castrillon, "Tools and dataflow-based programming models for heterogeneous MPSoCs", In Workshop on Power-Efficient GPU and Many-core Computing (PEGPUM'15) in conjunction with the HiPEAC Conference (invited talk), Jan 2015. [Bibtex & Downloads]
Tools and dataflow-based programming models for heterogeneous MPSoCs
×Reference
Jeronimo Castrillon, "Tools and dataflow-based programming models for heterogeneous MPSoCs", In Workshop on Power-Efficient GPU and Many-core Computing (PEGPUM'15) in conjunction with the HiPEAC Conference (invited talk), Jan 2015.
Bibtex
@Misc{castrillon2015pegpum,
Title={Tools and dataflow-based programming models for heterogeneous MPSoCs},
Author={Castrillon, Jeronimo},
HowPublished={Workshop on Power-Efficient GPU and Many-core Computing (PEGPUM'15) in conjunction with the HiPEAC Conference (invited talk)},
Year={2015},
Month=jan,
Location={Amsterdam, The Netherlands},
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/150121_castrillon_pegpum.pdf}
}Downloads
150121_castrillon_pegpum [PDF]
Related Paths
Permalink
- Jeronimo Castrillon, "Simulation and Estimation for MPSoC Programming Tools", In Proceeding: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'15), in conjunction with the HiPEAC Conference (keynote), Jan 2015. [Bibtex & Downloads]
Simulation and Estimation for MPSoC Programming Tools
×Reference
Jeronimo Castrillon, "Simulation and Estimation for MPSoC Programming Tools", In Proceeding: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'15), in conjunction with the HiPEAC Conference (keynote), Jan 2015.
Bibtex
@InProceedings{castrillon2015rapido,
Title={Simulation and Estimation for MPSoC Programming Tools},
Author={Castrillon, Jeronimo},
Booktitle={Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'15), in conjunction with the HiPEAC Conference (keynote)},
Year={2015},
Month=jan,
Location={Amsterdam, The Netherlands},
url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/150121_castrillon_rapido.pdf}
}Downloads
150121_castrillon_rapido [PDF]
Related Paths
Permalink
- Christel Baier, Marcus Daum, Benjamin Engel, Hermann Härtig, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "Locks: Picking key methods for a scalable quantitative analysis", In Journal of Computer and System Sciences, Elsevier, vol. 81, no. 1, pp. 258–287, 2015. [doi] [Bibtex & Downloads]
Locks: Picking key methods for a scalable quantitative analysis
×Reference
Christel Baier, Marcus Daum, Benjamin Engel, Hermann Härtig, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "Locks: Picking key methods for a scalable quantitative analysis", In Journal of Computer and System Sciences, Elsevier, vol. 81, no. 1, pp. 258–287, 2015. [doi]
Bibtex
@article{baier2015locks,
title={Locks: Picking key methods for a scalable quantitative analysis},
author={Baier, Christel and Daum, Marcus and Engel, Benjamin and H{\"a}rtig, Hermann and Klein, Joachim and Kl{\"u}ppelholz, Sascha and M{\"a}rcker, Steffen and Tews, Hendrik and V{\"o}lp, Marcus},
journal={Journal of Computer and System Sciences},
volume={81},
number={1},
pages={258--287},
year={2015},
publisher={Elsevier},
doi={10.1016/j.jcss.2014.06.004}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Clemens Dubslaff, Christel Baier, Sascha Klüppelholz, "Probabilistic Model Checking for Feature-Oriented Systems", Chapter in Transactions on Aspect-Oriented Software Development XII, Springer, pp. 180–220, 2015. [doi] [Bibtex & Downloads]
Probabilistic Model Checking for Feature-Oriented Systems
×Reference
Clemens Dubslaff, Christel Baier, Sascha Klüppelholz, "Probabilistic Model Checking for Feature-Oriented Systems", Chapter in Transactions on Aspect-Oriented Software Development XII, Springer, pp. 180–220, 2015. [doi]
Bibtex
@incollection{dubslaff2015probabilistic,
title={Probabilistic Model Checking for Feature-Oriented Systems},
author={Dubslaff, Clemens and Baier, Christel and Kl{\"u}ppelholz, Sascha},
booktitle={Transactions on Aspect-Oriented Software Development XII},
pages={180--220},
year={2015},
publisher={Springer},
doi={10.1007/978-3-662-46734-3_5}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Marcus Völp, Michael Roitzsch, Hermann Härtig, "Towards an Interpretation of Mixed Criticality for Optimistic Scheduling", In Proceeding: 21st IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 15, 2015. [Bibtex & Downloads]
Towards an Interpretation of Mixed Criticality for Optimistic Scheduling
×Reference
Marcus Völp, Michael Roitzsch, Hermann Härtig, "Towards an Interpretation of Mixed Criticality for Optimistic Scheduling", In Proceeding: 21st IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 15, 2015.
Bibtex
@inproceedings{volp2015towards,
title={Towards an Interpretation of Mixed Criticality for Optimistic Scheduling},
author={V{\"o}lp, Marcus and Roitzsch, Michael and H{\"a}rtig, Hermann},
booktitle={21st IEEE Real-Time and Embedded Technology and Applications Symposium},
pages={15},
year={2015}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Nils Asmussen, Marcus Völp, "Heterogeneity Beyond Hybrid Architectures", In GI Fachgruppe Betriebssysteme - Frühjahrstreffen, 2015. [Bibtex & Downloads]
Heterogeneity Beyond Hybrid Architectures
×Reference
Nils Asmussen, Marcus Völp, "Heterogeneity Beyond Hybrid Architectures", In GI Fachgruppe Betriebssysteme - Frühjahrstreffen, 2015.
Bibtex
@misc{asmussenheterogeneity,
title={Heterogeneity Beyond Hybrid Architectures},
author={Asmussen, Nils and V{\"o}lp, Marcus},
howpublished={GI Fachgruppe Betriebssysteme - Frühjahrstreffen},
year={2015}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Götz, Nelly Bencomo, Robert France, "Devising the Future of the Models@ run. time Workshop", In ACM SIGSOFT Software Engineering Notes, ACM, vol. 40, no. 1, pp. 26–29, 2015. [doi] [Bibtex & Downloads]
Devising the Future of the Models@ run. time Workshop
×Reference
Sebastian Götz, Nelly Bencomo, Robert France, "Devising the Future of the Models@ run. time Workshop", In ACM SIGSOFT Software Engineering Notes, ACM, vol. 40, no. 1, pp. 26–29, 2015. [doi]
Bibtex
@article{gotz2015devising,
title={Devising the Future of the Models@ run. time Workshop},
author={G{\"o}tz, Sebastian and Bencomo, Nelly and France, Robert},
journal={ACM SIGSOFT Software Engineering Notes},
volume={40},
number={1},
pages={26--29},
year={2015},
publisher={ACM},
doi={10.1145/2693208.2693249}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomas Karnagel, Dirk Habich, Wolfgang Lehner, "Local vs. Global Optimization: Operator Placement Strategies in Heterogeneous Environments", In Computing, vol. 1, pp. O2, 2015. [Bibtex & Downloads]
Local vs. Global Optimization: Operator Placement Strategies in Heterogeneous Environments
×Reference
Tomas Karnagel, Dirk Habich, Wolfgang Lehner, "Local vs. Global Optimization: Operator Placement Strategies in Heterogeneous Environments", In Computing, vol. 1, pp. O2, 2015.
Bibtex
@article{karnagel1local,
title={Local vs. Global Optimization: Operator Placement Strategies in Heterogeneous Environments},
author={Karnagel, Tomas and Habich, Dirk and Lehner, Wolfgang},
journal={Computing},
volume={1},
pages={O2},
year={2015}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Ertel, Christof Fetzer, Pascal Felber, "Ohua: Implicit Dataflow Programming for Concurrent Systems", Proceedings of the Principles and Practices of Programming on The Java Platform, ACM, pp. 51–64, New York, NY, USA, 2015. [doi] [Bibtex & Downloads]
Ohua: Implicit Dataflow Programming for Concurrent Systems
×Reference
Sebastian Ertel, Christof Fetzer, Pascal Felber, "Ohua: Implicit Dataflow Programming for Concurrent Systems", Proceedings of the Principles and Practices of Programming on The Java Platform, ACM, pp. 51–64, New York, NY, USA, 2015. [doi]
Bibtex
@inproceedings{Ertel:2015:OID:2807426.2807431,
author={Sebastian Ertel and Christof Fetzer and Pascal Felber},
title={Ohua: Implicit Dataflow Programming for Concurrent Systems},
booktitle={Proceedings of the Principles and Practices of Programming on The Java Platform},
series={PPPJ '15},
year={2015},
isbn={978-1-4503-3712-0},
location={Melbourne, FL, USA},
pages={51--64},
numpages={14},
url={http://doi.acm.org/10.1145/2807426.2807431},
doi={10.1145/2807426.2807431},
acmid={2807431},
publisher={ACM},
address={New York, NY, USA},
}Downloads
ohua_pppj [PDF]
presentation_pppj [PDF]
Related Paths
Permalink
- Daniel Krähmann, Jana Schubert, Christel Baier, Clemens Dubslaff, "Ratio and weight quantiles", Chapter in Mathematical Foundations of Computer Science 2015, Springer, pp. 344–356, 2015. [Bibtex & Downloads]
Ratio and weight quantiles
×Reference
Daniel Krähmann, Jana Schubert, Christel Baier, Clemens Dubslaff, "Ratio and weight quantiles", Chapter in Mathematical Foundations of Computer Science 2015, Springer, pp. 344–356, 2015.
Bibtex
@incollection{krahmann2015ratio,
title={Ratio and weight quantiles},
author={Kr{\"a}hmann, Daniel and Schubert, Jana and Baier, Christel and Dubslaff, Clemens},
booktitle={Mathematical Foundations of Computer Science 2015},
pages={344--356},
year={2015},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Clemens Dubslaff, Christel Baier, "Quantitative Analysis of Communication Scenarios", Chapter in Formal Modeling and Analysis of Timed Systems, Springer, pp. 76–92, 2015. [Bibtex & Downloads]
Quantitative Analysis of Communication Scenarios
×Reference
Clemens Dubslaff, Christel Baier, "Quantitative Analysis of Communication Scenarios", Chapter in Formal Modeling and Analysis of Timed Systems, Springer, pp. 76–92, 2015.
Bibtex
@incollection{dubslaff2015quantitative,
title={Quantitative Analysis of Communication Scenarios},
author={Dubslaff, Clemens and Baier, Christel},
booktitle={Formal Modeling and Analysis of Timed Systems},
pages={76--92},
year={2015},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, "Reasoning About Cost-Utility Constraints in Probabilistic Models", Chapter in Reachability Problems, Springer, pp. 1–6, 2015. [Bibtex & Downloads]
Reasoning About Cost-Utility Constraints in Probabilistic Models
×Reference
Christel Baier, "Reasoning About Cost-Utility Constraints in Probabilistic Models", Chapter in Reachability Problems, Springer, pp. 1–6, 2015.
Bibtex
@incollection{baier2015reasoning,
title={Reasoning About Cost-Utility Constraints in Probabilistic Models},
author={Baier, Christel},
booktitle={Reachability Problems},
pages={1--6},
year={2015},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Joachim Klein, Christel Baier, Sascha Klüppelholz, "Compositional construction of most general controllers", In Acta Informatica, Springer, pp. 1–40, 2015. [Bibtex & Downloads]
Compositional construction of most general controllers
×Reference
Joachim Klein, Christel Baier, Sascha Klüppelholz, "Compositional construction of most general controllers", In Acta Informatica, Springer, pp. 1–40, 2015.
Bibtex
@article{klein2015compositional,
title={Compositional construction of most general controllers},
author={Klein, Joachim and Baier, Christel and Kl{\"u}ppelholz, Sascha},
journal={Acta Informatica},
pages={1--40},
year={2015},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Till Smejkal, Adam Lackorzynski, Benjamin Engel, Marcus Völp, "Transactional IPC in Fiasco. OC", In OSPERT 2015, pp. 19, 2015. [Bibtex & Downloads]
Transactional IPC in Fiasco. OC
×Reference
Till Smejkal, Adam Lackorzynski, Benjamin Engel, Marcus Völp, "Transactional IPC in Fiasco. OC", In OSPERT 2015, pp. 19, 2015.
Bibtex
@article{smejkal2015transactional,
title={Transactional IPC in Fiasco. OC},
author={Smejkal, Till and Lackorzynski, Adam and Engel, Benjamin and V{\"o}lp, Marcus},
journal={OSPERT 2015},
pages={19},
year={2015}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marco Salvalaglio, Rainer Backofen, Roberto Bergamaschini, Francesco Montalenti, Axel Voigt, "Faceting of equilibrium and metastable nanostructures: a Phase-Field model of surface diffusion tackling realistic shapes", In Crystal Growth & Design, ACS Publications, 2015. [Bibtex & Downloads]
Faceting of equilibrium and metastable nanostructures: a Phase-Field model of surface diffusion tackling realistic shapes
×Reference
Marco Salvalaglio, Rainer Backofen, Roberto Bergamaschini, Francesco Montalenti, Axel Voigt, "Faceting of equilibrium and metastable nanostructures: a Phase-Field model of surface diffusion tackling realistic shapes", In Crystal Growth & Design, ACS Publications, 2015.
Bibtex
@article{salvalaglio2015faceting,
title={Faceting of equilibrium and metastable nanostructures: a Phase-Field model of surface diffusion tackling realistic shapes},
author={Salvalaglio, Marco and Backofen, Rainer and Bergamaschini, Roberto and Montalenti, Francesco and Voigt, Axel},
journal={Crystal Growth \& Design},
year={2015},
publisher={ACS Publications}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- T. Witkowski, S. Ling, S. Praetorius, A. Voigt, "Software concepts and numerical algorithms for a scalable adaptive parallel finite element method", In Advances in Computational Mathematics, Springer, pp. 1–33, 2015. [Bibtex & Downloads]
Software concepts and numerical algorithms for a scalable adaptive parallel finite element method
×Reference
T. Witkowski, S. Ling, S. Praetorius, A. Voigt, "Software concepts and numerical algorithms for a scalable adaptive parallel finite element method", In Advances in Computational Mathematics, Springer, pp. 1–33, 2015.
Bibtex
@article{witkowski2015software,
title={Software concepts and numerical algorithms for a scalable adaptive parallel finite element method},
author={Witkowski, T and Ling, S and Praetorius, S and Voigt, A},
journal={Advances in Computational Mathematics},
pages={1--33},
year={2015},
publisher={Springer}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Volp, Nils Asmussen, Hermann Hartig, Benedikt Nothen, Gerhard Fettweis, "Towards dependable CPS infrastructures: Architectural and operating-system challenges", In Proceeding: Emerging Technologies & Factory Automation (ETFA), 2015 IEEE 20th Conference on, pp. 1–8, 2015. [Bibtex & Downloads]
Towards dependable CPS infrastructures: Architectural and operating-system challenges
×Reference
Marcus Volp, Nils Asmussen, Hermann Hartig, Benedikt Nothen, Gerhard Fettweis, "Towards dependable CPS infrastructures: Architectural and operating-system challenges", In Proceeding: Emerging Technologies & Factory Automation (ETFA), 2015 IEEE 20th Conference on, pp. 1–8, 2015.
Bibtex
@inproceedings{volp2015towards,
title={Towards dependable CPS infrastructures: Architectural and operating-system challenges},
author={Volp, Marcus and Asmussen, Nils and Hartig, Hermann and Nothen, Benedikt and Fettweis, Gerhard},
booktitle={Emerging Technologies \& Factory Automation (ETFA), 2015 IEEE 20th Conference on},
pages={1--8},
year={2015},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Nils Asmussen, Marcus Volp, Benedikt Nothen, Annett Ungethum, "Demo abstract: Taming many heterogeneous cores", In Proceeding: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015 IEEE, pp. 329–329, 2015. [Bibtex & Downloads]
Demo abstract: Taming many heterogeneous cores
×Reference
Nils Asmussen, Marcus Volp, Benedikt Nothen, Annett Ungethum, "Demo abstract: Taming many heterogeneous cores", In Proceeding: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015 IEEE, pp. 329–329, 2015.
Bibtex
@inproceedings{asmussen2015demo,
title={Demo abstract: Taming many heterogeneous cores},
author={Asmussen, Nils and Volp, Marcus and Nothen, Benedikt and Ungethum, Annett},
booktitle={Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015 IEEE},
pages={329--329},
year={2015},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogeneity", In Computers & Fluids, vol. 117, pp. 114 - 124, 2015. [doi] [Bibtex & Downloads]
Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogeneity
×Reference
Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogeneity", In Computers & Fluids, vol. 117, pp. 114 - 124, 2015. [doi]
Bibtex
@article{Huismann2015114,
title={Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogeneity},
journal={Computers & Fluids},
volume={117},
pages={114 - 124},
year={2015},
issn={0045-7930},
doi={http://dx.doi.org/10.1016/j.compfluid.2015.05.012},
url={http://www.sciencedirect.com/science/article/pii/S004579301500167X},
author={Immo Huismann and Jörg Stiller and Jochen Fröhlich},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Hahnel, Hermann Hartig, "Demo abstract: An energy/utility demo-Energy-aware resource scheduling under utility considerations", In Proceeding: 2015 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 330, 2015. [Bibtex & Downloads]
Demo abstract: An energy/utility demo-Energy-aware resource scheduling under utility considerations
×Reference
Marcus Hahnel, Hermann Hartig, "Demo abstract: An energy/utility demo-Energy-aware resource scheduling under utility considerations", In Proceeding: 2015 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 330, 2015.
Bibtex
@inproceedings{hahnel2015demo,
title={Demo abstract: An energy/utility demo-Energy-aware resource scheduling under utility considerations},
author={Hahnel, Marcus and Hartig, Hermann},
booktitle={2015 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)},
pages={330},
year={2015},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tobias Kempe, Alvaro Aguilera, Wolfgang Nagel, Jochen Fröhlich, "Performance of a projection method for incompressible flows on heterogeneous hardware", In Computers & Fluids, Elsevier, vol. 121, pp. 37–43, 2015. [Bibtex & Downloads]
Performance of a projection method for incompressible flows on heterogeneous hardware
×Reference
Tobias Kempe, Alvaro Aguilera, Wolfgang Nagel, Jochen Fröhlich, "Performance of a projection method for incompressible flows on heterogeneous hardware", In Computers & Fluids, Elsevier, vol. 121, pp. 37–43, 2015.
Bibtex
@article{kempe2015performance,
title={Performance of a projection method for incompressible flows on heterogeneous hardware},
author={Kempe, Tobias and Aguilera, Alvaro and Nagel, Wolfgang and Fr{\"o}hlich, Jochen},
journal={Computers \& Fluids},
volume={121},
pages={37--43},
year={2015},
publisher={Elsevier}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Vinay Suryaprakash, Jesper Moller, Gerhard Fettweis, "On the modeling and analysis of heterogeneous radio access networks using a Poisson cluster process", In Wireless Communications, IEEE Transactions on, IEEE, vol. 14, no. 2, pp. 1035–1047, 2015. [Bibtex & Downloads]
On the modeling and analysis of heterogeneous radio access networks using a Poisson cluster process
×Reference
Vinay Suryaprakash, Jesper Moller, Gerhard Fettweis, "On the modeling and analysis of heterogeneous radio access networks using a Poisson cluster process", In Wireless Communications, IEEE Transactions on, IEEE, vol. 14, no. 2, pp. 1035–1047, 2015.
Bibtex
@article{suryaprakash2015modeling,
title={On the modeling and analysis of heterogeneous radio access networks using a Poisson cluster process},
author={Suryaprakash, Vinay and Moller, Jesper and Fettweis, Gerhard},
journal={Wireless Communications, IEEE Transactions on},
volume={14},
number={2},
pages={1035--1047},
year={2015},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Vinay Suryaprakash, Peter Rost, Gerhard Fettweis, "Are Heterogeneous Cloud-Based Radio Access Networks Cost Effective?", In Selected Areas in Communications, IEEE Journal on, IEEE, vol. 33, no. 10, pp. 2239–2251, 2015. [Bibtex & Downloads]
Are Heterogeneous Cloud-Based Radio Access Networks Cost Effective?
×Reference
Vinay Suryaprakash, Peter Rost, Gerhard Fettweis, "Are Heterogeneous Cloud-Based Radio Access Networks Cost Effective?", In Selected Areas in Communications, IEEE Journal on, IEEE, vol. 33, no. 10, pp. 2239–2251, 2015.
Bibtex
@article{suryaprakash2015heterogeneous,
title={Are Heterogeneous Cloud-Based Radio Access Networks Cost Effective?},
author={Suryaprakash, Vinay and Rost, Peter and Fettweis, Gerhard},
journal={Selected Areas in Communications, IEEE Journal on},
volume={33},
number={10},
pages={2239--2251},
year={2015},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogenity", In Computers & Fluids, Elsevier, 2015. [Bibtex & Downloads]
Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogenity
×Reference
Immo Huismann, Jörg Stiller, Jochen Fröhlich, "Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogenity", In Computers & Fluids, Elsevier, 2015.
Bibtex
@article{huismann2015two,
title={Two-level parallelization of a fluid mechanics algorithm exploiting hardware heterogenity},
author={Huismann, Immo and Stiller, J{\"o}rg and Fr{\"o}hlich, Jochen},
journal={Computers \& Fluids},
year={2015},
publisher={Elsevier}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomás Babiak, Frantisek Blahoudek, Alexandre Duret-Lutz, Joachim Klein, Jan Kretínský, David Müller, David Parker, Jan Strejcek, "The Hanoi Omega-Automata Format", In Proceeding: Proc. of the 27th Conference on Computer Aided Verification, Part I (CAV), Springer, vol. 9206, pp. 479–486, 2015. [Bibtex & Downloads]
The Hanoi Omega-Automata Format
×Reference
Tomás Babiak, Frantisek Blahoudek, Alexandre Duret-Lutz, Joachim Klein, Jan Kretínský, David Müller, David Parker, Jan Strejcek, "The Hanoi Omega-Automata Format", In Proceeding: Proc. of the 27th Conference on Computer Aided Verification, Part I (CAV), Springer, vol. 9206, pp. 479–486, 2015.
Bibtex
@inproceedings{BBDKKMPS15,
author = {Tom{\'{a}}s Babiak, Frantisek Blahoudek, Alexandre Duret-Lutz, Joachim Klein, Jan Kret{\'{\i}}nsk{\'{y}}, David M{\"u}ller, David Parker, Jan Strejcek},
title = {The {H}anoi Omega-Automata Format},
booktitle = {Proc. of the 27th Conference on Computer Aided Verification, Part I (CAV)},
year = {2015},
pages = {479--486},
series = {Lecture Notes in Computer Science},
volume = {9206},
publisher = {Springer},
ee = {http://dx.doi.org/10.1007/978-3-319-21690-4_31}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Peter Rost, Ignacio Berberana, Andreas Maeder, Henning Paul, Vinay Suryaprakash, Matthew Valenti, Dirk Wübben, Armin Dekorsy, Gerhard Fettweis, "Benefits and challenges of virtualization in 5G radio access networks", In IEEE Communications Magazine, IEEE, vol. 53, no. 12, pp. 75–82, 2015. [Bibtex & Downloads]
Benefits and challenges of virtualization in 5G radio access networks
×Reference
Peter Rost, Ignacio Berberana, Andreas Maeder, Henning Paul, Vinay Suryaprakash, Matthew Valenti, Dirk Wübben, Armin Dekorsy, Gerhard Fettweis, "Benefits and challenges of virtualization in 5G radio access networks", In IEEE Communications Magazine, IEEE, vol. 53, no. 12, pp. 75–82, 2015.
Bibtex
@article{rost2015benefits,
title={Benefits and challenges of virtualization in 5G radio access networks},
author={Rost, Peter and Berberana, Ignacio and Maeder, Andreas and Paul, Henning and Suryaprakash, Vinay and Valenti, Matthew and W{\"u}bben, Dirk and Dekorsy, Armin and Fettweis, Gerhard},
journal={IEEE Communications Magazine},
volume={53},
number={12},
pages={75--82},
year={2015},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Maximilian Matthé, Luciano Leonel Mendes, Nicola Michailow, Dan Zhang, Gerhard Fettweis, "Widely linear estimation for space-time-coded GFDM in low-latency applications", In IEEE Transactions on Communications, IEEE, vol. 63, no. 11, pp. 4501–4509, 2015. [Bibtex & Downloads]
Widely linear estimation for space-time-coded GFDM in low-latency applications
×Reference
Maximilian Matthé, Luciano Leonel Mendes, Nicola Michailow, Dan Zhang, Gerhard Fettweis, "Widely linear estimation for space-time-coded GFDM in low-latency applications", In IEEE Transactions on Communications, IEEE, vol. 63, no. 11, pp. 4501–4509, 2015.
Bibtex
@article{matthe2015widely,
title={Widely linear estimation for space-time-coded GFDM in low-latency applications},
author={Matth{\'e}, Maximilian and Mendes, Luciano Leonel and Michailow, Nicola and Zhang, Dan and Fettweis, Gerhard},
journal={IEEE Transactions on Communications},
volume={63},
number={11},
pages={4501--4509},
year={2015},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
2014
- Jeronimo Castrillon, "Compiler Flow for Processors and Systems", In Winter School on Design, Programming and Applications of Multi Processor System on Chip (invited talk), Nov 2014. [Bibtex & Downloads]
Compiler Flow for Processors and Systems
×Reference
Jeronimo Castrillon, "Compiler Flow for Processors and Systems", In Winter School on Design, Programming and Applications of Multi Processor System on Chip (invited talk), Nov 2014.
Bibtex
@Misc{castrillon2015tunis,
Title={Compiler Flow for Processors and Systems},
Author={Castrillon, Jeronimo},
HowPublished={Winter School on Design, Programming and Applications of Multi Processor System on Chip (invited talk)},
Year={2014},
Month=nov,
Location={Tunis, Tunisia},
url={https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/141127_castrillon_compilers.pdf}
}Downloads
141127_castrillon_compilers [PDF]
Related Paths
Permalink
- Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "Probabilistic Software Product Line Model Checking", In Presentation, April 2014. [Bibtex & Downloads]
Probabilistic Software Product Line Model Checking
×Reference
Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "Probabilistic Software Product Line Model Checking", In Presentation, April 2014.
Bibtex
@misc{DKB14,
Author={Clemens Dubslaff and Sascha Kl{\"{u}}ppelholz and Christel Baier},
Title={Probabilistic Software Product Line Model Checking},
Booktitle={12th Workshop on Quantitative Aspects of Programming Languages and Systems (QAPL)},
Howpublished={Presentation},
Month={April},
Year={2014}}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Benedikt Noethen, Oliver Arnold, Esther Perez Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matus, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, others, "10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS", In Proceeding: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pp. 188–189, 2014. [doi] [Bibtex & Downloads]
10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
×Reference
Benedikt Noethen, Oliver Arnold, Esther Perez Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matus, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, others, "10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS", In Proceeding: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pp. 188–189, 2014. [doi]
Bibtex
@inproceedings{noethen201410,
title={10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS},
author={Noethen, Benedikt and Arnold, Oliver and Adeva, Esther Perez and Seifert, Tobias and Fischer, Erik and Kunze, Steffen and Matus, Emil and Fettweis, Gerhard and Eisenreich, Holger and Ellguth, Georg and others},
booktitle={Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International},
pages={188--189},
year={2014},
organization={IEEE},
doi={10.1109/ISSCC.2014.6757394}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Christel Baier, Clemens Dubslaff, Sascha Klüppelholz, "Trade-off analysis meets probabilistic model checking", Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS), pp. 1, 2014. [doi] [Bibtex & Downloads]
Trade-off analysis meets probabilistic model checking
×Reference
Christel Baier, Clemens Dubslaff, Sascha Klüppelholz, "Trade-off analysis meets probabilistic model checking", Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS), pp. 1, 2014. [doi]
Bibtex
@inproceedings{baier2014trade,
title={Trade-off analysis meets probabilistic model checking},
author={Baier, Christel and Dubslaff, Clemens and Kl{\"u}ppelholz, Sascha},
booktitle={Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS)},
pages={1},
year={2014},
organization={ACM},
doi={10.1145/2603088.2603089}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Clemens Dubslaff, Joachim Klein, Sascha Klüppelholz, Sascha Wunderlich, "Probabilistic model checking for energy-utility analysis", Chapter in Horizons of the Mind. A Tribute to Prakash Panangaden, Springer, pp. 96–123, 2014. [doi] [Bibtex & Downloads]
Probabilistic model checking for energy-utility analysis
×Reference
Christel Baier, Clemens Dubslaff, Joachim Klein, Sascha Klüppelholz, Sascha Wunderlich, "Probabilistic model checking for energy-utility analysis", Chapter in Horizons of the Mind. A Tribute to Prakash Panangaden, Springer, pp. 96–123, 2014. [doi]
Bibtex
@incollection{baier2014probabilistic,
title={Probabilistic model checking for energy-utility analysis},
author={Baier, Christel and Dubslaff, Clemens and Klein, Joachim and Kl{\"u}ppelholz, Sascha and Wunderlich, Sascha},
booktitle={Horizons of the Mind. A Tribute to Prakash Panangaden},
pages={96--123},
year={2014},
publisher={Springer},
doi={10.1007/978-3-319-06880-0_5}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Clemens Dubslaff, Sascha Klüppelholz, Linda Leuschner, "Energy-utility analysis for resilient systems using probabilistic model checking", Chapter in Application and Theory of Petri Nets and Concurrency, Springer, pp. 20–39, 2014. [doi] [Bibtex & Downloads]
Energy-utility analysis for resilient systems using probabilistic model checking
×Reference
Christel Baier, Clemens Dubslaff, Sascha Klüppelholz, Linda Leuschner, "Energy-utility analysis for resilient systems using probabilistic model checking", Chapter in Application and Theory of Petri Nets and Concurrency, Springer, pp. 20–39, 2014. [doi]
Bibtex
@incollection{baier2014energy,
title={Energy-utility analysis for resilient systems using probabilistic model checking},
author={Baier, Christel and Dubslaff, Clemens and Kl{\"u}ppelholz, Sascha and Leuschner, Linda},
booktitle={Application and Theory of Petri Nets and Concurrency},
pages={20--39},
year={2014},
publisher={Springer},
doi={10.1007/978-3-319-07734-5_2}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Clemens Dubslaff, Sascha Klüppelholz, Marcus Daum, Joachim Klein, Steffen Märcker, Sascha Wunderlich, "Probabilistic Model Checking and Non-standard Multi-objective Reasoning", Chapter in Fundamental Approaches to Software Engineering, Springer, pp. 1–16, 2014. [doi] [Bibtex & Downloads]
Probabilistic Model Checking and Non-standard Multi-objective Reasoning
×Reference
Christel Baier, Clemens Dubslaff, Sascha Klüppelholz, Marcus Daum, Joachim Klein, Steffen Märcker, Sascha Wunderlich, "Probabilistic Model Checking and Non-standard Multi-objective Reasoning", Chapter in Fundamental Approaches to Software Engineering, Springer, pp. 1–16, 2014. [doi]
Bibtex
@incollection{baier2014probabilistic,
title={Probabilistic Model Checking and Non-standard Multi-objective Reasoning},
author={Baier, Christel and Dubslaff, Clemens and Kl{\"u}ppelholz, Sascha and Daum, Marcus and Klein, Joachim and M{\"a}rcker, Steffen and Wunderlich, Sascha},
booktitle={Fundamental Approaches to Software Engineering},
pages={1--16},
year={2014},
publisher={Springer},
doi={10.1007/978-3-642-54804-8_1}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Joachim Klein, Sascha Klüppelholz, "Synthesis of Reo Connectors for Strategies and Controllers", In Fundamenta Informaticae, IOS Press, vol. 130, no. 1, pp. 1–20, 2014. [doi] [Bibtex & Downloads]
Synthesis of Reo Connectors for Strategies and Controllers
×Reference
Christel Baier, Joachim Klein, Sascha Klüppelholz, "Synthesis of Reo Connectors for Strategies and Controllers", In Fundamenta Informaticae, IOS Press, vol. 130, no. 1, pp. 1–20, 2014. [doi]
Bibtex
@article{baier2014synthesis,
title={Synthesis of Reo Connectors for Strategies and Controllers},
author={Baier, Christel and Klein, Joachim and Kl{\"u}ppelholz, Sascha},
journal={Fundamenta Informaticae},
volume={130},
number={1},
pages={1--20},
year={2014},
publisher={IOS Press},
doi={10.3233/FI-2014-980}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Joachim Klein, Sascha Klüppelholz, Sascha Wunderlich, "Weight monitoring with linear temporal logic: Complexity and decidability", Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS), pp. 11, 2014. [doi] [Bibtex & Downloads]
Weight monitoring with linear temporal logic: Complexity and decidability
×Reference
Christel Baier, Joachim Klein, Sascha Klüppelholz, Sascha Wunderlich, "Weight monitoring with linear temporal logic: Complexity and decidability", Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS), pp. 11, 2014. [doi]
Bibtex
@inproceedings{baier2014weight,
title={Weight monitoring with linear temporal logic: Complexity and decidability},
author={Baier, Christel and Klein, Joachim and Kl{\"u}ppelholz, Sascha and Wunderlich, Sascha},
booktitle={Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS)},
pages={11},
year={2014},
organization={ACM},
doi={10.1145/2603088.2603162}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, "Computing conditional probabilities in Markovian models efficiently", Chapter in Tools and Algorithms for the Construction and Analysis of Systems, Springer, pp. 515–530, 2014. [doi] [Bibtex & Downloads]
Computing conditional probabilities in Markovian models efficiently
×Reference
Christel Baier, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, "Computing conditional probabilities in Markovian models efficiently", Chapter in Tools and Algorithms for the Construction and Analysis of Systems, Springer, pp. 515–530, 2014. [doi]
Bibtex
@incollection{baier2014computing,
title={Computing conditional probabilities in Markovian models efficiently},
author={Baier, Christel and Klein, Joachim and Kl{\"u}ppelholz, Sascha and M{\"a}rcker, Steffen},
booktitle={Tools and Algorithms for the Construction and Analysis of Systems},
pages={515--530},
year={2014},
publisher={Springer},
doi={10.1007/978-3-642-54862-8_43}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Marcus Daum, Clemens Dubslaff, Joachim Klein, Sascha Klüppelholz, "Energy-utility quantiles", Chapter in NASA Formal Methods, Springer, pp. 285–299, 2014. [doi] [Bibtex & Downloads]
Energy-utility quantiles
×Reference
Christel Baier, Marcus Daum, Clemens Dubslaff, Joachim Klein, Sascha Klüppelholz, "Energy-utility quantiles", Chapter in NASA Formal Methods, Springer, pp. 285–299, 2014. [doi]
Bibtex
@incollection{baier2014energy,
title={Energy-utility quantiles},
author={Baier, Christel and Daum, Marcus and Dubslaff, Clemens and Klein, Joachim and Kl{\"u}ppelholz, Sascha},
booktitle={NASA Formal Methods},
pages={285--299},
year={2014},
publisher={Springer},
doi={10.1007/978-3-319-06200-6_24}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "Probabilistic Model Checking for Energy Analysis in Software Product Lines", In Proceeding: Proc. of the 13th International Conference on Modularity (MODULARITY), ACM, pp. 169–180, 2014. [Bibtex & Downloads]
Probabilistic Model Checking for Energy Analysis in Software Product Lines
×Reference
Clemens Dubslaff, Sascha Klüppelholz, Christel Baier, "Probabilistic Model Checking for Energy Analysis in Software Product Lines", In Proceeding: Proc. of the 13th International Conference on Modularity (MODULARITY), ACM, pp. 169–180, 2014.
Bibtex
@inproceedings{DKB14_MODULARITY,
author={Clemens Dubslaff and Sascha Kl{\"u}ppelholz and Christel Baier},
title={Probabilistic Model Checking for Energy Analysis in Software Product Lines},
booktitle={Proc. of the 13th International Conference on Modularity (MODULARITY)},
year={2014},
pages={169--180},
publisher={ACM},
ee={http://doi.acm.org/10.1145/2577080.2577095},
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Ely Levy, Amnon Barak, Amnon Shiloh, Matthias Lieber, Carsten Weinhold, Hermann Härtig, "Overhead of a decentralized gossip algorithm on the performance of HPC applications", Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, pp. 10, 2014. [doi] [Bibtex & Downloads]
Overhead of a decentralized gossip algorithm on the performance of HPC applications
×Reference
Ely Levy, Amnon Barak, Amnon Shiloh, Matthias Lieber, Carsten Weinhold, Hermann Härtig, "Overhead of a decentralized gossip algorithm on the performance of HPC applications", Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, pp. 10, 2014. [doi]
Bibtex
@inproceedings{levy2014overhead,
title={Overhead of a decentralized gossip algorithm on the performance of HPC applications},
author={Levy, Ely and Barak, Amnon and Shiloh, Amnon and Lieber, Matthias and Weinhold, Carsten and H{\"a}rtig, Hermann},
booktitle={Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers},
pages={10},
year={2014},
organization={ACM},
doi={10.1145/2612262.2612271}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Immo Huismann, Lars Haupt, Jörg Stiller, Jochen Fröhlich, "Sum factorization of the static condensed Helmholtz equation in a three-dimensional spectral element discretization", In PAMM, Wiley Online Library, vol. 14, no. 1, pp. 969–970, 2014. [doi] [Bibtex & Downloads]
Sum factorization of the static condensed Helmholtz equation in a three-dimensional spectral element discretization
×Reference
Immo Huismann, Lars Haupt, Jörg Stiller, Jochen Fröhlich, "Sum factorization of the static condensed Helmholtz equation in a three-dimensional spectral element discretization", In PAMM, Wiley Online Library, vol. 14, no. 1, pp. 969–970, 2014. [doi]
Bibtex
@article{huismann2014sum,
title={Sum factorization of the static condensed Helmholtz equation in a three-dimensional spectral element discretization},
author={Huismann, Immo and Haupt, Lars and Stiller, J{\"o}rg and Fr{\"o}hlich, Jochen},
journal={PAMM},
volume={14},
number={1},
pages={969--970},
year={2014},
publisher={Wiley Online Library},
doi={10.1002/pamm.201410465}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Adam Lackorzynski, Marcus Völp, Alexander Warg, "Flat but trustworthy: security aspects in flattened hierarchical scheduling", In ACM SIGBED Review, ACM, vol. 11, no. 2, pp. 8–12, 2014. [Bibtex & Downloads]
Flat but trustworthy: security aspects in flattened hierarchical scheduling
×Reference
Adam Lackorzynski, Marcus Völp, Alexander Warg, "Flat but trustworthy: security aspects in flattened hierarchical scheduling", In ACM SIGBED Review, ACM, vol. 11, no. 2, pp. 8–12, 2014.
Bibtex
@article{lackorzynski2014flat,
title={Flat but trustworthy: security aspects in flattened hierarchical scheduling},
author={Lackorzynski, Adam and V{\"o}lp, Marcus and Warg, Alexander},
journal={ACM SIGBED Review},
volume={11},
number={2},
pages={8--12},
year={2014},
publisher={ACM}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Joachim Klein, David Müller, Christel Baier, Sascha Klüppelholz, "Are Good-for-Games Automata Good for Probabilistic Model Checking?", Chapter in Language and Automata Theory and Applications, Springer, pp. 453–465, 2014. [doi] [Bibtex & Downloads]
Are Good-for-Games Automata Good for Probabilistic Model Checking?
×Reference
Joachim Klein, David Müller, Christel Baier, Sascha Klüppelholz, "Are Good-for-Games Automata Good for Probabilistic Model Checking?", Chapter in Language and Automata Theory and Applications, Springer, pp. 453–465, 2014. [doi]
Bibtex
@incollection{klein2014good,
title={Are Good-for-Games Automata Good for Probabilistic Model Checking?},
author={Klein, Joachim and M{\"u}ller, David and Baier, Christel and Kl{\"u}ppelholz, Sascha},
booktitle={Language and Automata Theory and Applications},
pages={453--465},
year={2014},
publisher={Springer},
doi={10.1007/978-3-319-04921-2_37}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Matthias Lieber, Wolfgang E Nagel, "Scalable high-quality 1D partitioning", In Proceeding: High Performance Computing & Simulation (HPCS), 2014 International Conference on, pp. 112–119, 2014. [doi] [Bibtex & Downloads]
Scalable high-quality 1D partitioning
×Reference
Matthias Lieber, Wolfgang E Nagel, "Scalable high-quality 1D partitioning", In Proceeding: High Performance Computing & Simulation (HPCS), 2014 International Conference on, pp. 112–119, 2014. [doi]
Bibtex
@inproceedings{lieber2014scalable,
title={Scalable high-quality 1D partitioning},
author={Lieber, Matthias and Nagel, Wolfgang E},
booktitle={High Performance Computing & Simulation (HPCS), 2014 International Conference on},
pages={112--119},
year={2014},
organization={IEEE},
doi={10.1109/hpcsim.2014.6903676},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Matthias Lieber, Wolfgang E Nagel, Hartmut Mix, "Scalability Tuning of the Load Balancing and Coupling Framework FD4", In Proceeding: NIC Symposium 2014, vol. 47, pp. 363-370, 2014. [Bibtex & Downloads]
Scalability Tuning of the Load Balancing and Coupling Framework FD4
×Reference
Matthias Lieber, Wolfgang E Nagel, Hartmut Mix, "Scalability Tuning of the Load Balancing and Coupling Framework FD4", In Proceeding: NIC Symposium 2014, vol. 47, pp. 363-370, 2014.
Bibtex
@inproceedings{lieber2014scalability,
title={Scalability Tuning of the Load Balancing and Coupling Framework FD4},
author={Lieber, Matthias and Nagel, Wolfgang E and Mix, Hartmut},
year={2014},
booktitle={NIC Symposium 2014},
series={NIC Series},
volume={47},
pages={363-370},
isbn={978-3-89336-933-1}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Völp, "What if we would degrade LO tasks in mixed-criticality systems?", In Proceeding: 20th IEEE Real-Time and Embedded Technology and Applications Symposium-Work in Progress Session (RTAS-WIP 2014), Berlin, Germany, 2014. [Bibtex & Downloads]
What if we would degrade LO tasks in mixed-criticality systems?
×Reference
Marcus Völp, "What if we would degrade LO tasks in mixed-criticality systems?", In Proceeding: 20th IEEE Real-Time and Embedded Technology and Applications Symposium-Work in Progress Session (RTAS-WIP 2014), Berlin, Germany, 2014.
Bibtex
@inproceedings{volp2014if,
title={What if we would degrade LO tasks in mixed-criticality systems?},
author={V{\"o}lp, Marcus},
booktitle={20th IEEE Real-Time and Embedded Technology and Applications Symposium-Work in Progress Session (RTAS-WIP 2014), Berlin, Germany},
year={2014}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Volp, Marcus Hahnel, Adam Lackorzynski, "Has energy surpassed timeliness? Scheduling energy-constrained mixed-criticality systems", In Proceeding: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th, pp. 275–284, 2014. [doi] [Bibtex & Downloads]
Has energy surpassed timeliness? Scheduling energy-constrained mixed-criticality systems
×Reference
Marcus Volp, Marcus Hahnel, Adam Lackorzynski, "Has energy surpassed timeliness? Scheduling energy-constrained mixed-criticality systems", In Proceeding: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th, pp. 275–284, 2014. [doi]
Bibtex
@inproceedings{volp2014has,
title={Has energy surpassed timeliness? Scheduling energy-constrained mixed-criticality systems},
author={Volp, Marcus and Hahnel, Marcus and Lackorzynski, Adam},
booktitle={Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th},
pages={275--284},
year={2014},
organization={IEEE},
doi={10.1109/RTAS.2014.6926009}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Völp, Michael Roitzsch, "Elastic Manycores", In Proceeding: Euro-Par 2013: Parallel Processing Workshops, pp. 749–758, 2014. [doi] [Bibtex & Downloads]
Elastic Manycores
×Reference
Marcus Völp, Michael Roitzsch, "Elastic Manycores", In Proceeding: Euro-Par 2013: Parallel Processing Workshops, pp. 749–758, 2014. [doi]
Bibtex
@inproceedings{volp2014elastic,
title={Elastic Manycores},
author={V{\"o}lp, Marcus and Roitzsch, Michael},
booktitle={Euro-Par 2013: Parallel Processing Workshops},
pages={749--758},
year={2014},
organization={Springer},
doi={10.1007/978-3-642-54420-0_73}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Nathalie Bertrand, Patricia Bouyer, Thomas Brihaye, Quentin Menet, Christel Baier, Marcus Größer, Marcin Jurdzinski, "Stochastic Timed Automata", In Logical Methods in Computer Science (LMCS), vol. 10, no. 4, pp. 1–73, 2014. [Bibtex & Downloads]
Stochastic Timed Automata
×Reference
Nathalie Bertrand, Patricia Bouyer, Thomas Brihaye, Quentin Menet, Christel Baier, Marcus Größer, Marcin Jurdzinski, "Stochastic Timed Automata", In Logical Methods in Computer Science (LMCS), vol. 10, no. 4, pp. 1–73, 2014.
Bibtex
@article{LMCS14,
author = {Nathalie Bertrand, Patricia Bouyer, Thomas Brihaye, Quentin Menet, Christel Baier, Marcus Gr\"o{\ss}er, Marcin Jurdzinski},
title = {Stochastic Timed Automata},
year = {2014},
journal = {Logical Methods in Computer Science (LMCS)},
volume = {10},
number = {4},
pages = {1--73},
ee = {http://dx.doi.org/10.2168/LMCS-10(4:6)2014}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Oliver Arnold, Sebastian Haas, Gerhard Fettweis, Benjamin Schlegel, Thomas Kissinger, Tomas Karnagel, Wolfgang Lehner, "HASHI: An Application-Specific Instruction Set Extension for Hashing", In ADMS@ VLDB, pp. 25–33, 2014. [Bibtex & Downloads]
HASHI: An Application-Specific Instruction Set Extension for Hashing
×Reference
Oliver Arnold, Sebastian Haas, Gerhard Fettweis, Benjamin Schlegel, Thomas Kissinger, Tomas Karnagel, Wolfgang Lehner, "HASHI: An Application-Specific Instruction Set Extension for Hashing", In ADMS@ VLDB, pp. 25–33, 2014.
Bibtex
@article{arnold2014hashi,
title={HASHI: An Application-Specific Instruction Set Extension for Hashing},
author={Arnold, Oliver and Haas, Sebastian and Fettweis, Gerhard and Schlegel, Benjamin and Kissinger, Thomas and Karnagel, Tomas and Lehner, Wolfgang},
journal={ADMS@ VLDB},
pages={25--33},
year={2014}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Oliver Arnold, Sebastian Haas, Gerhard Fettweis, Benjamin Schlegel, Thomas Kissinger, Wolfgang Lehner, "An Application-specific Instruction Set for Accelerating Set-oriented Database Primitives", Proceedings of the 2014 ACM SIGMOD International Conference on Management of Data, ACM, pp. 767–778, New York, NY, USA, 2014. [doi] [Bibtex & Downloads]
An Application-specific Instruction Set for Accelerating Set-oriented Database Primitives
×Reference
Oliver Arnold, Sebastian Haas, Gerhard Fettweis, Benjamin Schlegel, Thomas Kissinger, Wolfgang Lehner, "An Application-specific Instruction Set for Accelerating Set-oriented Database Primitives", Proceedings of the 2014 ACM SIGMOD International Conference on Management of Data, ACM, pp. 767–778, New York, NY, USA, 2014. [doi]
Bibtex
@inproceedings{Arnold:2014:AIS:2588555.2593677,
author={Arnold, Oliver and Haas, Sebastian and Fettweis, Gerhard and Schlegel, Benjamin and Kissinger, Thomas and Lehner, Wolfgang},
title={An Application-specific Instruction Set for Accelerating Set-oriented Database Primitives},
booktitle={Proceedings of the 2014 ACM SIGMOD International Conference on Management of Data},
series={SIGMOD '14},
year={2014},
isbn={978-1-4503-2376-5},
location={Snowbird, Utah, USA},
pages={767--778},
numpages={12},
url={http://doi.acm.org/10.1145/2588555.2593677},
doi={10.1145/2588555.2593677},
acmid={2593677},
publisher={ACM},
address={New York, NY, USA},
keywords={customizable processors, hardware/software-codesign, instruction set extensions},
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomas Karnagel, Dirk Habich, Benjamin Schlegel, Wolfgang Lehner, "Heterogeneity-Aware Operator Placement in Column-Store DBMS", In Datenbank-Spektrum, Springer, vol. 14, no. 3, pp. 211–221, 2014. [doi] [Bibtex & Downloads]
Heterogeneity-Aware Operator Placement in Column-Store DBMS
×Reference
Tomas Karnagel, Dirk Habich, Benjamin Schlegel, Wolfgang Lehner, "Heterogeneity-Aware Operator Placement in Column-Store DBMS", In Datenbank-Spektrum, Springer, vol. 14, no. 3, pp. 211–221, 2014. [doi]
Bibtex
@article{karnagel2014heterogeneity,
title={Heterogeneity-Aware Operator Placement in Column-Store DBMS},
author={Karnagel, Tomas and Habich, Dirk and Schlegel, Benjamin and Lehner, Wolfgang},
journal={Datenbank-Spektrum},
volume={14},
number={3},
pages={211--221},
year={2014},
publisher={Springer},
doi={10.1007/s13222-014-0167-9}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomas Karnagel, Roman Dementiev, Ravi Rajwar, Konrad Lai, Thomas Legler, Benjamin Schlegel, Wolfgang Lehner, "Improving in-memory database index performance with Intel\textregistered Transactional Synchronization Extensions", In Proceeding: High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, pp. 476–487, 2014. [doi] [Bibtex & Downloads]
Improving in-memory database index performance with Intel\textregistered Transactional Synchronization Extensions
×Reference
Tomas Karnagel, Roman Dementiev, Ravi Rajwar, Konrad Lai, Thomas Legler, Benjamin Schlegel, Wolfgang Lehner, "Improving in-memory database index performance with Intel\textregistered Transactional Synchronization Extensions", In Proceeding: High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, pp. 476–487, 2014. [doi]
Bibtex
@inproceedings{karnagel2014improving,
title={Improving in-memory database index performance with Intel{\textregistered} Transactional Synchronization Extensions},
author={Karnagel, Tomas and Dementiev, Roman and Rajwar, Ravi and Lai, Konrad and Legler, Thomas and Schlegel, Benjamin and Lehner, Wolfgang},
booktitle={High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on},
pages={476--487},
year={2014},
organization={IEEE},
doi={10.1109/HPCA.2014.6835957}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomas Karnagel, Matthias Hille, Mario Ludwig, Dirk Habich, Wolfgang Lehner, Max Heimel, Volker Markl, "Demonstrating efficient query processing in heterogeneous environments", Proceedings of the 2014 ACM SIGMOD international conference on Management of data, pp. 693–696, 2014. [doi] [Bibtex & Downloads]
Demonstrating efficient query processing in heterogeneous environments
×Reference
Tomas Karnagel, Matthias Hille, Mario Ludwig, Dirk Habich, Wolfgang Lehner, Max Heimel, Volker Markl, "Demonstrating efficient query processing in heterogeneous environments", Proceedings of the 2014 ACM SIGMOD international conference on Management of data, pp. 693–696, 2014. [doi]
Bibtex
@inproceedings{karnagel2014demonstrating,
title={Demonstrating efficient query processing in heterogeneous environments},
author={Karnagel, Tomas and Hille, Matthias and Ludwig, Mario and Habich, Dirk and Lehner, Wolfgang and Heimel, Max and Markl, Volker},
booktitle={Proceedings of the 2014 ACM SIGMOD international conference on Management of data},
pages={693--696},
year={2014},
organization={ACM},
doi={10.1145/2588555.2594526}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Ertel, Pascal Felber, "A Framework for the Dynamic Evolution of Highly-available Dataflow Programs", Proceedings of the 15th International Middleware Conference, ACM, pp. 157–168, New York, NY, USA, 2014. [doi] [Bibtex & Downloads]
A Framework for the Dynamic Evolution of Highly-available Dataflow Programs
×Reference
Sebastian Ertel, Pascal Felber, "A Framework for the Dynamic Evolution of Highly-available Dataflow Programs", Proceedings of the 15th International Middleware Conference, ACM, pp. 157–168, New York, NY, USA, 2014. [doi]
Bibtex
@inproceedings{Ertel:2014:FDE:2663165.2663320,
author={Sebastian Ertel and Pascal Felber},
title={A Framework for the Dynamic Evolution of Highly-available Dataflow Programs},
booktitle={Proceedings of the 15th International Middleware Conference},
series={Middleware '14},
year={2014},
isbn={978-1-4503-2785-5},
location={Bordeaux, France},
pages={157--168},
numpages={12},
url={http://doi.acm.org/10.1145/2663165.2663320},
doi={10.1145/2663165.2663320},
acmid={2663320},
publisher={ACM},
address={New York, NY, USA},
}Downloads
update_paper [PDF]
middleware_2014 [PDF]
Related Paths
Permalink
- John Thompson, Xiaohu Ge, Hsiao-Chun Wu, Ralf Irmer, Hong Jiang, Gerhard Fettweis, Siavash Alamouti, "5G wireless communication systems: prospects and challenges Part 2", In IEEE Communications Magazine, no. 52, pp. 24–25, 2014. [Bibtex & Downloads]
5G wireless communication systems: prospects and challenges Part 2
×Reference
John Thompson, Xiaohu Ge, Hsiao-Chun Wu, Ralf Irmer, Hong Jiang, Gerhard Fettweis, Siavash Alamouti, "5G wireless communication systems: prospects and challenges Part 2", In IEEE Communications Magazine, no. 52, pp. 24–25, 2014.
Bibtex
@article{thompson20145g,
title={5G wireless communication systems: prospects and challenges Part 2},
author={Thompson, John and Ge, Xiaohu and Wu, Hsiao-Chun and Irmer, Ralf and Jiang, Hong and Fettweis, Gerhard and Alamouti, Siavash},
journal={IEEE Communications Magazine},
number={52},
pages={24--25},
year={2014}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Gerhard P Fettweis, "The tactile internet: Applications and challenges", In Vehicular Technology Magazine, IEEE, IEEE, vol. 9, no. 1, pp. 64–70, 2014. [Bibtex & Downloads]
The tactile internet: Applications and challenges
×Reference
Gerhard P Fettweis, "The tactile internet: Applications and challenges", In Vehicular Technology Magazine, IEEE, IEEE, vol. 9, no. 1, pp. 64–70, 2014.
Bibtex
@article{fettweis2014tactile,
title={The tactile internet: Applications and challenges},
author={Fettweis, Gerhard P},
journal={Vehicular Technology Magazine, IEEE},
volume={9},
number={1},
pages={64--70},
year={2014},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Resilience Path
Permalink
- M. Hahnel, H. Hartig, "Heterogeneity by the numbers", In HotPower, 2014. [Bibtex & Downloads]
Heterogeneity by the numbers
×Reference
M. Hahnel, H. Hartig, "Heterogeneity by the numbers", In HotPower, 2014.
Bibtex
@article{hahnel2014heterogeneity,
title={Heterogeneity by the numbers},
author={Hahnel, M and Hartig, H},
journal={HotPower},
year={2014}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, HAEC, HAEC, Orchestration Path, HAEC
Permalink
- Dirk Habich, Stefanie Gahrig, Wolfgang Lehner, "Towards Optimal Execution of Density-based Clustering on Heterogeneous Hardware.", In Proceeding: BigMine, pp. 104–119, 2014. [Bibtex & Downloads]
Towards Optimal Execution of Density-based Clustering on Heterogeneous Hardware.
×Reference
Dirk Habich, Stefanie Gahrig, Wolfgang Lehner, "Towards Optimal Execution of Density-based Clustering on Heterogeneous Hardware.", In Proceeding: BigMine, pp. 104–119, 2014.
Bibtex
@inproceedings{habich2014towards,
title={Towards Optimal Execution of Density-based Clustering on Heterogeneous Hardware.},
author={Habich, Dirk and Gahrig, Stefanie and Lehner, Wolfgang},
booktitle={BigMine},
pages={104--119},
year={2014}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Orchestration Path, HAEC
Permalink
- Albrecht Fehske, Henrik Klessig, Jens Voigt, Gerhard Fettweis, "Flow-level models for capacity planning and management in interference-coupled wireless data networks", In IEEE Communications Magazine, IEEE, vol. 52, no. 2, pp. 164–171, 2014. [Bibtex & Downloads]
Flow-level models for capacity planning and management in interference-coupled wireless data networks
×Reference
Albrecht Fehske, Henrik Klessig, Jens Voigt, Gerhard Fettweis, "Flow-level models for capacity planning and management in interference-coupled wireless data networks", In IEEE Communications Magazine, IEEE, vol. 52, no. 2, pp. 164–171, 2014.
Bibtex
@article{fehske2014flow,
title={Flow-level models for capacity planning and management in interference-coupled wireless data networks},
author={Fehske, Albrecht and Klessig, Henrik and Voigt, Jens and Fettweis, Gerhard},
journal={IEEE Communications Magazine},
volume={52},
number={2},
pages={164--171},
year={2014},
publisher={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
2013
- Adam Lackorzynski, Benjamin Engel, Marcus Völp, "PredictableCoherentCachingwithIncoherentCaches", Proceedingsof15thReal-TimeLinuxWorkshop, Lugano-Manno, Switzerland, 10/2013. [Bibtex & Downloads]
PredictableCoherentCachingwithIncoherentCaches
×Reference
Adam Lackorzynski, Benjamin Engel, Marcus Völp, "PredictableCoherentCachingwithIncoherentCaches", Proceedingsof15thReal-TimeLinuxWorkshop, Lugano-Manno, Switzerland, 10/2013.
Bibtex
@inproceedings{Lackorzynski13:predictable-caching,
author={Adam Lackorzynski and Benjamin Engel and Marcus Völp},
title=,
booktitle=,
address={Lugano-Manno, Switzerland},
year={ 2013 },
month={ 10 },
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Benjamin Schlegel, Tomas Karnagel, Tim Kiefer, Wolfgang Lehner, "Scalable frequent itemset mining on many-core processors", Proceedings of the Ninth International Workshop on Data Management on New Hardware, pp. 3, 2013. [doi] [Bibtex & Downloads]
Scalable frequent itemset mining on many-core processors
×Reference
Benjamin Schlegel, Tomas Karnagel, Tim Kiefer, Wolfgang Lehner, "Scalable frequent itemset mining on many-core processors", Proceedings of the Ninth International Workshop on Data Management on New Hardware, pp. 3, 2013. [doi]
Bibtex
@inproceedings{schlegel2013scalable,
title={Scalable frequent itemset mining on many-core processors},
author={Schlegel, Benjamin and Karnagel, Tomas and Kiefer, Tim and Lehner, Wolfgang},
booktitle={Proceedings of the Ninth International Workshop on Data Management on New Hardware},
pages={3},
year={2013},
organization={ACM},
doi={10.1145/2485278.2485281}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Christel Baier, "Quantitative Analysis of Randomized Distributed Systems and Probabilistic Automata", Chapter in Algebraic Informatics, Springer, pp. 4–5, 2013. [doi] [Bibtex & Downloads]
Quantitative Analysis of Randomized Distributed Systems and Probabilistic Automata
×Reference
Christel Baier, "Quantitative Analysis of Randomized Distributed Systems and Probabilistic Automata", Chapter in Algebraic Informatics, Springer, pp. 4–5, 2013. [doi]
Bibtex
@incollection{baier2013quantitative,
title={Quantitative Analysis of Randomized Distributed Systems and Probabilistic Automata},
author={Baier, Christel},
booktitle={Algebraic Informatics},
pages={4--5},
year={2013},
publisher={Springer},
doi={10.1007/978-3-642-40663-8_2}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Benjamin Engel, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "A Probabilistic Quantitative Analysis of Probabilistic-Write/Copy-Select.", In Proceeding: NASA Formal Methods, pp. 307–321, 2013. [doi] [Bibtex & Downloads]
A Probabilistic Quantitative Analysis of Probabilistic-Write/Copy-Select.
×Reference
Christel Baier, Benjamin Engel, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "A Probabilistic Quantitative Analysis of Probabilistic-Write/Copy-Select.", In Proceeding: NASA Formal Methods, pp. 307–321, 2013. [doi]
Bibtex
@inproceedings{baier2013probabilistic,
title={A Probabilistic Quantitative Analysis of Probabilistic-Write/Copy-Select.},
author={Baier, Christel and Engel, Benjamin and Kl{\"u}ppelholz, Sascha and M{\"a}rcker, Steffen and Tews, Hendrik and V{\"o}lp, Marcus},
booktitle={NASA Formal Methods},
pages={307--321},
year={2013},
organization={Springer},
doi={10.1007/978-3-642-38088-4_21}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Hermann Härtig, Marcus Völp, Marcus Hähnel, "The case for practical multi-resource and multi-level scheduling based on Energy/Utility.", In Proceeding: RTCSA, pp. 175–182, 2013. [doi] [Bibtex & Downloads]
The case for practical multi-resource and multi-level scheduling based on Energy/Utility.
×Reference
Hermann Härtig, Marcus Völp, Marcus Hähnel, "The case for practical multi-resource and multi-level scheduling based on Energy/Utility.", In Proceeding: RTCSA, pp. 175–182, 2013. [doi]
Bibtex
@inproceedings{hartig2013case,
title={The case for practical multi-resource and multi-level scheduling based on Energy/Utility.},
author={H{\"a}rtig, Hermann and V{\"o}lp, Marcus and H{\"a}hnel, Marcus},
booktitle={RTCSA},
pages={175--182},
year={2013},
doi={10.1109/RTCSA.2013.6732217}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Johannes Israel, John Martinovic, Andreas Fischer, Michael Jenning, Lukas Landau, "Optimal antenna positioning for wireless board-to-board communication using a butler matrix beamforming network", In Proceeding: Smart Antennas (WSA), 2013 17th International ITG Workshop on, pp. 1–7, 2013. [Bibtex & Downloads]
Optimal antenna positioning for wireless board-to-board communication using a butler matrix beamforming network
×Reference
Johannes Israel, John Martinovic, Andreas Fischer, Michael Jenning, Lukas Landau, "Optimal antenna positioning for wireless board-to-board communication using a butler matrix beamforming network", In Proceeding: Smart Antennas (WSA), 2013 17th International ITG Workshop on, pp. 1–7, 2013.
Bibtex
@inproceedings{israel2013optimal,
title={Optimal antenna positioning for wireless board-to-board communication using a butler matrix beamforming network},
author={Israel, Johannes and Martinovic, John and Fischer, Andreas and Jenning, Michael and Landau, Lukas},
booktitle={Smart Antennas (WSA), 2013 17th International ITG Workshop on},
pages={1--7},
year={2013},
organization={VDE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Hähnel, Björn Döbel, Marcus Völp, Hermann Härtig, "eBond: energy saving in heterogeneous RAIN", Proceedings of the fourth international conference on Future energy systems, pp. 193–202, 2013. [Bibtex & Downloads]
eBond: energy saving in heterogeneous RAIN
×Reference
Marcus Hähnel, Björn Döbel, Marcus Völp, Hermann Härtig, "eBond: energy saving in heterogeneous RAIN", Proceedings of the fourth international conference on Future energy systems, pp. 193–202, 2013.
Bibtex
@inproceedings{hahnel2013ebond,
title={eBond: energy saving in heterogeneous RAIN},
author={H{\"a}hnel, Marcus and D{\"o}bel, Bj{\"o}rn and V{\"o}lp, Marcus and H{\"a}rtig, Hermann},
booktitle={Proceedings of the fourth international conference on Future energy systems},
pages={193--202},
year={2013},
organization={ACM}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Hahnel, Marcus Volp, Bjorn Dobel, Hermann Hartig, "The potential of energy/utility-accrual scheduling", In Proceeding: Advanced Information Networking and Applications Workshops (WAINA), 2013 27th International Conference on, pp. 1636–1641, 2013. [Bibtex & Downloads]
The potential of energy/utility-accrual scheduling
×Reference
Marcus Hahnel, Marcus Volp, Bjorn Dobel, Hermann Hartig, "The potential of energy/utility-accrual scheduling", In Proceeding: Advanced Information Networking and Applications Workshops (WAINA), 2013 27th International Conference on, pp. 1636–1641, 2013.
Bibtex
@inproceedings{hahnel2013potential,
title={The potential of energy/utility-accrual scheduling},
author={Hahnel, Marcus and Volp, Marcus and Dobel, Bjorn and Hartig, Hermann},
booktitle={Advanced Information Networking and Applications Workshops (WAINA), 2013 27th International Conference on},
pages={1636--1641},
year={2013},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Michael Ummels, Christel Baier, "Computing quantiles in Markov reward models", In Proceeding: Foundations of Software Science and Computation Structures, pp. 353–368, 2013. [doi] [Bibtex & Downloads]
Computing quantiles in Markov reward models
×Reference
Michael Ummels, Christel Baier, "Computing quantiles in Markov reward models", In Proceeding: Foundations of Software Science and Computation Structures, pp. 353–368, 2013. [doi]
Bibtex
@inproceedings{ummels2013computing,
title={Computing quantiles in Markov reward models},
author={Ummels, Michael and Baier, Christel},
booktitle={Foundations of Software Science and Computation Structures},
pages={353--368},
year={2013},
organization={Springer},
doi={10.1007/978-3-642-37075-5_23}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Marcus Völp, Adam Lackorzynski, Hermann Härtig, "On the expressiveness of fixed priority scheduling contexts for mixed criticality scheduling", In Proc. WMC, RTSS, pp. 13–18, 2013. [Bibtex & Downloads]
On the expressiveness of fixed priority scheduling contexts for mixed criticality scheduling
×Reference
Marcus Völp, Adam Lackorzynski, Hermann Härtig, "On the expressiveness of fixed priority scheduling contexts for mixed criticality scheduling", In Proc. WMC, RTSS, pp. 13–18, 2013.
Bibtex
@article{volp2013expressiveness,
title={On the expressiveness of fixed priority scheduling contexts for mixed criticality scheduling},
author={V{\"o}lp, Marcus and Lackorzynski, Adam and H{\"a}rtig, Hermann},
journal={Proc. WMC, RTSS},
pages={13--18},
year={2013}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Marcus Volp, Benjamin Engel, C. Hamann, Hermann Hartig, "On confidentiality-preserving real-time locking protocols", In Proceeding: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th, pp. 153–162, 2013. [doi] [Bibtex & Downloads]
On confidentiality-preserving real-time locking protocols
×Reference
Marcus Volp, Benjamin Engel, C. Hamann, Hermann Hartig, "On confidentiality-preserving real-time locking protocols", In Proceeding: Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th, pp. 153–162, 2013. [doi]
Bibtex
@inproceedings{volp2013confidentiality,
title={On confidentiality-preserving real-time locking protocols},
author={Volp, Marcus and Engel, Benjamin and Hamann, C and Hartig, Hermann},
booktitle={Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th},
pages={153--162},
year={2013},
organization={IEEE},
doi={10.1109/RTAS.2013.6531088}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Nils Asmussen, Hermann Härtig, Marcus Völp, "Turning x86 into a Hardware Simulator for Future Manycores", Proceedings of the 3rd Workshop on Systems for Future Multicore Architectures, 2013. [Bibtex & Downloads]
Turning x86 into a Hardware Simulator for Future Manycores
×Reference
Nils Asmussen, Hermann Härtig, Marcus Völp, "Turning x86 into a Hardware Simulator for Future Manycores", Proceedings of the 3rd Workshop on Systems for Future Multicore Architectures, 2013.
Bibtex
@inproceedings{asmussen2013turning,
title={Turning x86 into a Hardware Simulator for Future Manycores},
author={Asmussen, Nils and H{\"a}rtig, Hermann and V{\"o}lp, Marcus},
booktitle={Proceedings of the 3rd Workshop on Systems for Future Multicore Architectures},
year={2013}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tobias Hilbrich, Bronis R. de Supinski, Wolfgang E. Nagel, Joachim Protze, Christel Baier, Matthias S. Muller, "Distributed wait state tracking for runtime MPI deadlock detection", In Proceeding: High Performance Computing, Networking, Storage and Analysis (SC), 2013 International Conference for, pp. 1–12, 2013. [doi] [Bibtex & Downloads]
Distributed wait state tracking for runtime MPI deadlock detection
×Reference
Tobias Hilbrich, Bronis R. de Supinski, Wolfgang E. Nagel, Joachim Protze, Christel Baier, Matthias S. Muller, "Distributed wait state tracking for runtime MPI deadlock detection", In Proceeding: High Performance Computing, Networking, Storage and Analysis (SC), 2013 International Conference for, pp. 1–12, 2013. [doi]
Bibtex
@inproceedings{hilbrich2013distributed,
title={Distributed wait state tracking for runtime MPI deadlock detection},
author={Hilbrich, Tobias and de Supinski, Bronis R. and Nagel, Wolfgang E. and Protze, Joachim and Baier, Christel and Muller, Matthias S.},
booktitle={High Performance Computing, Networking, Storage and Analysis (SC), 2013 International Conference for},
pages={1--12},
year={2013},
organization={IEEE},
doi={10.1145/2503210.2503237}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Tomas Karnagel, Dirk Habich, Benjamin Schlegel, Wolfgang Lehner, "The HELLS-join: a heterogeneous stream join for extremely large windows", Proceedings of the Ninth International Workshop on Data Management on New Hardware, pp. 2, 2013. [doi] [Bibtex & Downloads]
The HELLS-join: a heterogeneous stream join for extremely large windows
×Reference
Tomas Karnagel, Dirk Habich, Benjamin Schlegel, Wolfgang Lehner, "The HELLS-join: a heterogeneous stream join for extremely large windows", Proceedings of the Ninth International Workshop on Data Management on New Hardware, pp. 2, 2013. [doi]
Bibtex
@inproceedings{karnagel2013hells,
title={The HELLS-join: a heterogeneous stream join for extremely large windows},
author={Karnagel, Tomas and Habich, Dirk and Schlegel, Benjamin and Lehner, Wolfgang},
booktitle={Proceedings of the Ninth International Workshop on Data Management on New Hardware},
pages={2},
year={2013},
organization={ACM},
doi={10.1145/2485278.2485280}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Tomas Karnagel, Benjamin Schlegel, Dirk Habich, Wolfgang Lehner, "Stream Join Processing on Heterogeneous Processors.", In Proceeding: BTW Workshops, pp. 17–26, 2013. [Bibtex & Downloads]
Stream Join Processing on Heterogeneous Processors.
×Reference
Tomas Karnagel, Benjamin Schlegel, Dirk Habich, Wolfgang Lehner, "Stream Join Processing on Heterogeneous Processors.", In Proceeding: BTW Workshops, pp. 17–26, 2013.
Bibtex
@inproceedings{karnagel2013stream,
title={Stream Join Processing on Heterogeneous Processors.},
author={Karnagel, Tomas and Schlegel, Benjamin and Habich, Dirk and Lehner, Wolfgang},
booktitle={BTW Workshops},
pages={17--26},
year={2013}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Sebastian Ertel, Michael J. Beckerle, "Dynamic Development Support for Highly Concurrent Programs in the Ohua Data Flow Engine", In Proceeding: Second Workshop on Languages for the Multicore Era (Co-located with ECOOP'13), 2013. [Bibtex & Downloads]
Dynamic Development Support for Highly Concurrent Programs in the Ohua Data Flow Engine
×Reference
Sebastian Ertel, Michael J. Beckerle, "Dynamic Development Support for Highly Concurrent Programs in the Ohua Data Flow Engine", In Proceeding: Second Workshop on Languages for the Multicore Era (Co-located with ECOOP'13), 2013.
Bibtex
@inproceedings{Ertel:Lame:2013,
author={Sebastian Ertel and Michael J. Beckerle},
title={Dynamic Development Support for Highly Concurrent Programs in the Ohua Data Flow Engine},
booktitle={Second Workshop on Languages for the Multicore Era (Co-located with ECOOP'13)},
series={LaME'13},
year={2013},
location={Montpellier, France},
url={http://lame2013.dei.uc.pt/}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Oliver Arnold, Emil Matus, Benedikt Noethen, Friedrich Pauls, Gerhard Fettweis, "Towards elastic SDR architectures using dynamic task management", In Proceeding: Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE, pp. 1286–1289, 2013. [Bibtex & Downloads]
Towards elastic SDR architectures using dynamic task management
×Reference
Oliver Arnold, Emil Matus, Benedikt Noethen, Friedrich Pauls, Gerhard Fettweis, "Towards elastic SDR architectures using dynamic task management", In Proceeding: Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE, pp. 1286–1289, 2013.
Bibtex
@inproceedings{arnold2013towards,
title={Towards elastic SDR architectures using dynamic task management},
author={Arnold, Oliver and Matus, Emil and Noethen, Benedikt and Pauls, Friedrich and Fettweis, Gerhard},
booktitle={Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE},
pages={1286--1289},
year={2013},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Oliver Arnold, Benedikt Noethen, Gerhard Fettweis, "A Flexible Analytic Model for a Dynamic Task-Scheduling Unit for Heterogeneous MPSoCs", In Proceeding: International Conference on Advances in System Simulation (SIMUL'13), Venice Italy, vol. 27, no. 1.11, 2013. [Bibtex & Downloads]
A Flexible Analytic Model for a Dynamic Task-Scheduling Unit for Heterogeneous MPSoCs
×Reference
Oliver Arnold, Benedikt Noethen, Gerhard Fettweis, "A Flexible Analytic Model for a Dynamic Task-Scheduling Unit for Heterogeneous MPSoCs", In Proceeding: International Conference on Advances in System Simulation (SIMUL'13), Venice Italy, vol. 27, no. 1.11, 2013.
Bibtex
@inproceedings{arnold2013flexible,
title={A Flexible Analytic Model for a Dynamic Task-Scheduling Unit for Heterogeneous MPSoCs},
author={Arnold, Oliver and Noethen, Benedikt and Fettweis, Gerhard},
booktitle={International Conference on Advances in System Simulation (SIMUL'13), Venice Italy},
volume={27},
number={1.11},
year={2013}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Benedikt Noethen, Oliver Arnold, Gerhard Fettweis, "On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs", In Proceeding: System on Chip (SoC), 2013 International Symposium on, pp. 1–7, 2013. [Bibtex & Downloads]
On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs
×Reference
Benedikt Noethen, Oliver Arnold, Gerhard Fettweis, "On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs", In Proceeding: System on Chip (SoC), 2013 International Symposium on, pp. 1–7, 2013.
Bibtex
@inproceedings{noethen2013impact,
title={On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs},
author={Noethen, Benedikt and Arnold, Oliver and Fettweis, Gerhard},
booktitle={System on Chip (SoC), 2013 International Symposium on},
pages={1--7},
year={2013},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Orchestration Path
Permalink
2012
- Benjamin Engel, Marcus Voelp, "First Experiences on PWCS synchronized Data Structures", In Proceeding: 14th Real Time Linux Workshop, October 2012. [Bibtex & Downloads]
First Experiences on PWCS synchronized Data Structures
×Reference
Benjamin Engel, Marcus Voelp, "First Experiences on PWCS synchronized Data Structures", In Proceeding: 14th Real Time Linux Workshop, October 2012.
Bibtex
@InProceedings{pwcs,
Title={First Experiences on PWCS synchronized Data Structures},
Author={Engel, Benjamin and Voelp, Marcus},
Booktitle={14th Real Time Linux Workshop},
Month={October},
Year={2012}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Álvaro Fernández-Díaz, Christel Baier, Clara Benac-Earle, Lars-Åke Fredlund, "Static Partial Order Reduction for Probabilistic Concurrent Systems" , Proceedings of the International Conference on Quantitative Evaluation of Systems (QEST), Sep 2012. [Bibtex & Downloads]
Static Partial Order Reduction for Probabilistic Concurrent Systems
×Reference
Álvaro Fernández-Díaz, Christel Baier, Clara Benac-Earle, Lars-Åke Fredlund, "Static Partial Order Reduction for Probabilistic Concurrent Systems" , Proceedings of the International Conference on Quantitative Evaluation of Systems (QEST), Sep 2012.
Bibtex
@InProceedings{ auto-key*fc,
author = {Fernández-Díaz, Álvaro and Baier, Christel and Benac-Earle, Clara and Fredlund, Lars-Åke},
title = {Static Partial Order Reduction for Probabilistic Concurrent Systems},
booktitle = {Proceedings of the International Conference on Quantitative Evaluation of Systems (QEST)},
month = sep,
year = {2012},
project = {B03}
}
Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Paolo Zuliani, Christel Baier, Edmund Melson Clarke, "Rare-event verification for stochastic hybrid systems" , Proceedings of the ACM International Conference on Hybrid Systems: Computation and Control (HSCC), Jul 2012. [Bibtex & Downloads]
Rare-event verification for stochastic hybrid systems
×Reference
Paolo Zuliani, Christel Baier, Edmund Melson Clarke, "Rare-event verification for stochastic hybrid systems" , Proceedings of the ACM International Conference on Hybrid Systems: Computation and Control (HSCC), Jul 2012.
Bibtex
@InProceedings{ auto-key*fd,
author = {Paolo Zuliani and Christel Baier and Edmund Melson Clarke},
title = {Rare-event verification for stochastic hybrid systems},
booktitle = {Proceedings of the ACM International Conference on Hybrid Systems: Computation and Control (HSCC)},
month = jul,
year = {2012},
project = {B03}
}
Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Tomáš Brázdil, Marcus Größer, Antonín Kučera, "Stochastic game logic" , In Acta Informatica, vol. 49, no. 4, pp. 203-224, Jun 2012. [Bibtex & Downloads]
Stochastic game logic
×Reference
Christel Baier, Tomáš Brázdil, Marcus Größer, Antonín Kučera, "Stochastic game logic" , In Acta Informatica, vol. 49, no. 4, pp. 203-224, Jun 2012.
Bibtex
@Article{ auto-key*fe,
author = {Christel Baier and Tomáš Brázdil and Marcus Größer and Antonín Kučera},
title = {Stochastic game logic},
journal = {Acta Informatica},
volume = {49},
number = {4},
pages = {203-224},
month = jun,
year = {2012},
project = {B03}
}
Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Adam Lackorzyński, Alexander Warg, Marcus Völp, Hermann Härtig, "Flattening hierarchical scheduling", Proceedings of the tenth ACM international conference on Embedded software, pp. 93–102, 2012. [doi] [Bibtex & Downloads]
Flattening hierarchical scheduling
×Reference
Adam Lackorzyński, Alexander Warg, Marcus Völp, Hermann Härtig, "Flattening hierarchical scheduling", Proceedings of the tenth ACM international conference on Embedded software, pp. 93–102, 2012. [doi]
Bibtex
@inproceedings{lackorzynski2012flattening,
title={Flattening hierarchical scheduling},
author={Lackorzy{\'n}ski, Adam and Warg, Alexander and V{\"o}lp, Marcus and H{\"a}rtig, Hermann},
booktitle={Proceedings of the tenth ACM international conference on Embedded software},
pages={93--102},
year={2012},
organization={ACM},
doi={10.1145/2380356.2380376}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Christel Baier, Marcus Daum, Benjamin Engel, Hermann Härtig, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "Waiting for locks: How long does it usually take?", Springer, 2012. [doi] [Bibtex & Downloads]
Waiting for locks: How long does it usually take?
×Reference
Christel Baier, Marcus Daum, Benjamin Engel, Hermann Härtig, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "Waiting for locks: How long does it usually take?", Springer, 2012. [doi]
Bibtex
@book{baier2012waiting,
title={Waiting for locks: How long does it usually take?},
author={Baier, Christel and Daum, Marcus and Engel, Benjamin and H{\"a}rtig, Hermann and Klein, Joachim and Kl{\"u}ppelholz, Sascha and M{\"a}rcker, Steffen and Tews, Hendrik and V{\"o}lp, Marcus},
year={2012},
publisher={Springer},
doi={10.1007/978-3-642-32469-7_4}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Christel Baier, Marcus Daum, Benjamin Engel, Hermann Härtig, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "Chiefly Symmetric: Results on the Scalability
of Probabilistic Model Checking for Operating-System Code", In Proceeding: Proc. of the 7th Conference on
Systems Software Verification (SSV'12), vol. 102, pp. 156–166, 2012. [Bibtex & Downloads]
Chiefly Symmetric: Results on the Scalability of Probabilistic Model Checking for Operating-System Code
×Reference
Christel Baier, Marcus Daum, Benjamin Engel, Hermann Härtig, Joachim Klein, Sascha Klüppelholz, Steffen Märcker, Hendrik Tews, Marcus Völp, "Chiefly Symmetric: Results on the Scalability of Probabilistic Model Checking for Operating-System Code", In Proceeding: Proc. of the 7th Conference on Systems Software Verification (SSV'12), vol. 102, pp. 156–166, 2012.
Bibtex
@inproceedings{BDEHKKMTV-SSV12,
author = {Christel Baier, Marcus Daum, Benjamin Engel, Hermann H{\"a}rtig, Joachim Klein, Sascha Kl{\"u}ppelholz, Steffen M{\"a}rcker, Hendrik Tews and Marcus V{\"o}lp},
title = {Chiefly Symmetric: Results on the Scalability
of Probabilistic Model Checking for Operating-System Code},
booktitle = {Proc. of the 7th Conference on
Systems Software Verification (SSV'12)},
year = {2012},
pages = {156--166},
series = {Electronic Proceedings in Theoretical Computer Science},
volume = {102},
ee = {http://dx.doi.org/10.4204/EPTCS.102.14}
}Downloads
No Downloads available for this publication
Related Paths
HAEC, Orchestration Path, Resilience Path
Permalink
- Marcus Hähnel, Björn Döbel, Marcus Völp, Hermann Härtig, "Measuring energy consumption for short code paths using RAPL", In ACM SIGMETRICS Performance Evaluation Review, ACM, vol. 40, no. 3, pp. 13–17, 2012. [Bibtex & Downloads]
Measuring energy consumption for short code paths using RAPL
×Reference
Marcus Hähnel, Björn Döbel, Marcus Völp, Hermann Härtig, "Measuring energy consumption for short code paths using RAPL", In ACM SIGMETRICS Performance Evaluation Review, ACM, vol. 40, no. 3, pp. 13–17, 2012.
Bibtex
@article{hahnel2012measuring,
title={Measuring energy consumption for short code paths using RAPL},
author={H{\"a}hnel, Marcus and D{\"o}bel, Bj{\"o}rn and V{\"o}lp, Marcus and H{\"a}rtig, Hermann},
journal={ACM SIGMETRICS Performance Evaluation Review},
volume={40},
number={3},
pages={13--17},
year={2012},
publisher={ACM}
}Downloads
No Downloads available for this publication
Related Paths
Permalink
- Wolfgang Lehner, Gerhard Fettweis, "Technology Time Machine 2012-Paving the path for the future technology developments [includes 9 white papers]", In Proceeding: Technology Time Machine Symposium (TTM), 2012 IEEE, pp. 1–38, 2012. [Bibtex & Downloads]
Technology Time Machine 2012-Paving the path for the future technology developments [includes 9 white papers]
×Reference
Wolfgang Lehner, Gerhard Fettweis, "Technology Time Machine 2012-Paving the path for the future technology developments [includes 9 white papers]", In Proceeding: Technology Time Machine Symposium (TTM), 2012 IEEE, pp. 1–38, 2012.
Bibtex
@inproceedings{lehner2012technology,
title={Technology Time Machine 2012-Paving the path for the future technology developments [includes 9 white papers]},
author={Lehner, Wolfgang and Fettweis, Gerhard},
booktitle={Technology Time Machine Symposium (TTM), 2012 IEEE},
pages={1--38},
year={2012},
organization={IEEE}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, Resilience Path
Permalink
Previous Years
- Marcus Völp, Johannes Steinmetz, Marcus Hähnel, "Consolidate-to-Idle", In Proceeding: 19th Real-Time and Embedded Technology and Applications Symposium, vol. 19, pp. 9–12. [Bibtex & Downloads]
Consolidate-to-Idle
×Reference
Marcus Völp, Johannes Steinmetz, Marcus Hähnel, "Consolidate-to-Idle", In Proceeding: 19th Real-Time and Embedded Technology and Applications Symposium, vol. 19, pp. 9–12.
Bibtex
@inproceedings{volp19consolidate,
title={Consolidate-to-Idle},
author={V{\"o}lp, Marcus and Steinmetz, Johannes and H{\"a}hnel, Marcus},
booktitle={19th Real-Time and Embedded Technology and Applications Symposium},
volume={19},
pages={9--12}
}Downloads
No Downloads available for this publication
Related Paths
Orchestration Path, HAEC, Orchestration Path
Permalink
- Tobias Stumpf, Hermann Härtig, Eberle A Rambo, Rolf Ernst, "Cross-layer Resilience Mechanisms to Protect the Communication Path in Embedded Systems". [Bibtex & Downloads]
Cross-layer Resilience Mechanisms to Protect the Communication Path in Embedded Systems
×Reference
Tobias Stumpf, Hermann Härtig, Eberle A Rambo, Rolf Ernst, "Cross-layer Resilience Mechanisms to Protect the Communication Path in Embedded Systems".
Bibtex
@article{stumpfcross,
title={Cross-layer Resilience Mechanisms to Protect the Communication Path in Embedded Systems},
author={Stumpf, Tobias and H{\"a}rtig, Hermann and Rambo, Eberle A and Ernst, Rolf}
}Downloads
No Downloads available for this publication
Related Paths
Permalink